MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 41

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

Data Sheet
Cells of AAL5 VC will go to the packet reassembly process; when a packet completes in the packet reassembly
process, its handle is sent to the packet identification buffer. The packet identifier parses through the packet,
identifying various headers and extracting the identification key with which the packet will be searched for. The
packet identifier also consults the Next Header memory and the Profile Memory to decide what to do if it encounters
certain next header or option values.
Once the packet parser has assembled all of the necessary headers, it consults the initial search structure to
decide what to do with the packet. In the case of a voice packet, the structure should tell it to search in the binary
tree using a specific profile. It then passes the packet to the identification key hashing process. This process
performs CRC on the identification key and annexes the profile number to it to obtain a full 60-bit key, which is then
used to search for the packet in the binary tree.
When the correct node is found in the binary tree, that node points to a post-search confirmation structure. The
headers contained in this structure are then compared to the headers used initially to form the packet’s
identification key. In addition, the flow table is searched to verify whether the destination IP address of the packet
can be received on the current logical subnet. If both tests are passed, then the packet matches the post-search
confirmation structure, which then indicates what its destination should be. If the packet does not match, then it
keeps on being searched until it hits a post-search confirmation structure it matches with, or it hits the default
structure for its profile that gives it a default destination.
Network Packet
Buffer NET2-4
UTOPIA look-up: Searches for cells based on their VPI/VCI, establishes their destination, associates them to a Packet Reassembly Structure
or an RX AAL2 VC structure.
Packet to block conversion: Converts Ethernet or Packet over SONET packets into 48-byte cell blocks, padding at the end.
Packet Reassembly: Accumulates the cells on many VCs, checks for AAL5 errors, flags completion of packets.
Raw Cell Buffer
RAWCELL0-1
Reassembly
Packet
Packet Reassembly
Structure (1 per VC,
Ethernet/POS)
1 global in
NET1
Legend:
Zarlink Semiconductor Inc.
Figure 16 - Rx Flow 1
AAL5 VC Struct Base
cell FIFO
RX link B
cell FIFO
RX link A
(global)
(global)
Structure in Internal Memory
Structure in SSRAM A
Structure in SSRAM B
Structure in SSRAM C
Structure in SDRAM C
port A =
Ethernet/
POS
port A =
UTOPIA
UTOPIA look-up
port) UTOPIA0
table (1 per
conversion
Packet to
UTOPIA
look-up
block
Data propagation
Control propagation
Data+Control propagation
Structure Base Address or Index
Chip Process
Software Process
RX packet FIFO
UTOPIA RX B
UTOPIA RX A
Ethernet/POS
input FIFO
input FIFO
(global)
(global)
(global)
From link B
From link A
MT92220
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