MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 168

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

MT92220
Data Sheet
gpio_in[2]
‘0’
ct_mc
ct_mc_in
ct_c8_selected
MC Clock
mc_clock
ct_frame_selected
Generator
Figure 101 - Message Channel Circuit
12.3
Memory Controllers
The MT92220 uses 3 separate memory banks, each with its own memory controller. Memory bank A is used for
structures in the TX direction. Memory bank B is used for structures in the RX direction. Memory bank C is used by
the device’s network interface.
Each memory bank, A, B, or C can connect up to 4 external SSRAM chips, each ranging in size from 128K to 1M
bytes. However, the total size of SSRAM chips on each bank is limited to 2M bytes. Memory bank C can also
connect to one external SDRAM of either 16M or 32M bytes. Memory banks A and B are 16 bits wide, while bank C
is 32 bits wide. Because SDRAM devices are much more commonly found in 16-bit configuration, 2 devices can be
placed side by side. On memory bank C, the address and data pins are shared between the SSRAM and SDRAM
devices.
SSRAM must be pipelined or flow-through ZBT (Zero-Bus Turnaround) type memory.
To multiplex the accesses that all agents require of these memories, memory controllers are used. Each memory
controller grants the memory bus to the various agents within the chip, using a priority algorithm to make sure that
the agents that need the memory most urgently get it, and transforming these memory accesses into the correct pin
signals depending on the configuration of the memories.
The memory controller is responsible for generating even parity on the parity pins of the memories and detecting
that the parity is correctly received when data is read from the memory. To do so, it calculates even parity on all the
address bits and data bits used to generate each access. When reading from the memory, it performs the same
calculation in the opposite direction. Any errors in parity are reported to registers. To render parity generation and
detection more powerful, masks can be used, causing the memory controller to only calculate parity on some bits.
These masks are programmed in registers 230h to 234h.
Parity is calculated on all locations in memory except for the reception circular buffers, in which the parity bits are
used for underrun information. It is possible to override this and use parity even on these circular buffers through
control bits in registers.
The controller also makes sure that the SDRAMs used are refreshed often enough so as to ensure that data in
them is never corrupted. The refresh period is indicated in registers, and a limit value is placed on how far behind in
its refreshing the chip can afford to be. If the refresh mechanism falls behind by more than this number, a status
error will be reported. This is programmed in registers 398h and 39Ah.
Finally, the memory controller allows manual accesses to the SDRAM to be performed through registers, allowing
CPU accesses to perform the initialization sequence to the SDRAM.
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