MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 157

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

Data Sheet
11.0
The TDM interface on the MT92220 device is fully compatible with the H.110 bus and can be used to interface
either as bus master or as bus slave. It respects all of the major requirements of H.110, such as supporting up to 32
TDM streams running at 8 MHz (up to 4096 time slots), the possibility of running 16 of the streams at lower
frequencies (2 or 4 MHz), and the capability of passing 128 of the channels on H.110 in loopback.
The slave portion of the H.110 interface respects the timing requirements of this interface. It can sample the
incoming data from the ct_d pins 90 ns after the rising edge of the clock as per the spec (3/4 sampling), and it can
also sample on the falling edge (2/4 sampling) or rising edge of the clock (4/4 sampling). When driving its data, it
can tri-state its pins early (between 20 and 0 ns before the rising edge of the clock) or it can tri-state synchronously
on the rising edge of the clock. Both of these options allow flexibility in interoperation with other devices that are not
fully H.110 compliant.
ct_d_out (8M,ealry Z)
ct_d_out (4M,ealry Z)
ct_d_out (2M,ealry Z)
H.110 Interface
ct_d_out (8M)
ct_d_out (4M)
ct_d_out (2M)
ct_d_in (8M)
ct_d_in (4M)
ct_d_in (2M)
ct_frame
ct_c8
63.b3
63.b3
127.b6 127.b5 127.b4 127.b3 127.b2 127.b1 127.b0
127.b6 127.b5 127.b4 127.b3 127.b2 127.b1 127.b0
31.b1
31.b1
63.b2
63.b2
Figure 91 - TDM Bus Timing - ct_d
63.b1
63.b1
Zarlink Semiconductor Inc.
31.b0
31.b0
1/2 Period Sampling
3/4 Period Sampling
4/4 Period Sampling
63.b0
63.b0
MT92220
157