MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 167

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

Data Sheet
The second portion of the clock recovery circuit is concerned with actually generating the adap_ref signal. When
software reads the information placed in the buffer, it can calculate what is the rate of the clock that needs to be
generated. The generated clock is always mem_clk divided by a 16-bit integer and 16-bit fraction, which allows a
very high precision on the division (with mem_clk running at 50 MHz and a target clock speed of 8 kHz, it gives a
precision of 0.4 ppb). Software can program the integer and fraction by which it desires mem_clk to be divided by,
and the division will be performed in hardware. The adap_ref signal can then be output onto any of a number of
GPIOs on the chip, or to one of the ct_netref s: among other uses, it can be routed to an external PLL used to
multiply it up from 8 kHz to 16 MHz and then rerouted into the chip on the pll_clk pin.
ct_c8_selected
ct_frame_selected
vc_reference_a
vc_reference_b
ct_c8_a
ct_c8_b
ct_frame_a
ct_frame_b
‘0’/’1’
ct_netref1_in
ct_netref2_in
gpio_in[0]
gpio_in[1]
gpio_in[2]
gpio_in[3]
gpio_in[4]
gpio_in[5]
gpio_in[6]
gpio_in[7]
adapa_ref
adapb_ref
mc_clock
ct_mc_in
Pll_clk
Figure 100 - GPIO Functionality
Zarlink Semiconductor Inc.
and Level
Monitor
Edges
Internal_pll_clk
gpio[7:0],
ct_netref1,
ct_netref2
MT92220
167