MSC8101ADS Freescale Semiconductor / Motorola, MSC8101ADS Datasheet - Page 58

• Manufacturer Part Number: MSC8101ADS
• Description: MSC8101 APP DEV SYSTEM
• Manufacturer: Freescale Semiconductor / Motorola

Physical and Electrical Specifications
2.6.6
2-18
Number
44a
44b
44c
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
62
63
64
Read data strobe minimum assertion width
HACK read minimum assertion width
Read data strobe minimum deassertion width
HACK read minimum deassertion width
Read data strobe minimum deassertion width
reads
HACK minimum deassertion width after “Last Data Register” reads
Write data strobe minimum assertion width
HACK write minimum assertion width
Write data strobe minimum deassertion width
HACK write minimum deassertion width after ICR, CVR and Data Register
writes
Host data input minimum set-up time before write data strobe deassertion
Host data input minimum set-up time before HACK write deassertion
Host data input minimum hold time after write data strobe deassertion
Host data input minimum hold time after HACK write deassertion
Read data strobe minimum assertion to output data active from high
impedance
HACK read minimum assertion to output data active from high impedance
Read data strobe maximum assertion to output data valid
HACK read maximum assertion to output data valid
Read data strobe maximum deassertion to output data high impedance
HACK read maximum deassertion to output data high impedance
Output data minimum hold time after read data strobe deassertion
Output data minimum hold time after HACK read deassertion
HCS[1–2] minimum assertion to read data strobe assertion
HCS[1–2] minimum assertion to write data strobe assertion
HCS[1–2] maximum assertion to output data valid
HCS[1–2] minimum hold time after data strobe deassertion
HA[0–3], HRW minimum set-up time before data strobe assertion
•
•
HA[0–3], HRW minimum hold time after data strobe deassertion
Maximum delay from read data strobe deassertion to host request deassertion
for “Last Data Register” read
Maximum delay from write data strobe deassertion to host request deassertion
for “Last Data Register” write
Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1)
deassertion to HREQ assertion.
Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1)
assertion to HREQ deassertion
HDI16 Signals
Read
Write
5,6
5
, or between two consecutive CVR, ICR, or ISR reads
4
Table 2-19.
4, 5, 10
5,8,10
Characteristics
MSC8101 Technical Data, Rev. 19
8
4
Host Interface (HDI16) Timing
8
4
4
after “Last Data Register”
3
4
4
9
8
7
9
9
4
5,6
8
4
8
1, 2
(1.5 × T
(2.5 × T
(1.5 × T
(2.5 × T
(2.0 × T
(3.5 × T
(5.0 × T
(3.5 × T
Expression
(3.0 × T
T
T
C
C
—
—
—
—
—
—
—
—
—
—
+ 5.0
+ 5.0
C
C
C
C
C
C
C
C
C
) + 5.0
) + 5.0
) + 5.0
) + 5.0
) + 5.0
) + 5.0
) + 5.0
) + 5.0
) + 5
Freescale Semiconductor
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
Value
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0.0
5.0
5.0
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns