MSC8101ADS Freescale Semiconductor / Motorola, MSC8101ADS Datasheet - Page 5

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MSC8101ADS

Manufacturer Part Number
MSC8101ADS
Description
MSC8101 APP DEV SYSTEM
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Signals/Connections
The MSC8101 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and
Figure 1-2. Table 1-1 lists the functional groups, states the number of signal connections in each group, and
references the table that gives details on multiplexed signals within each group. Figure 1-1 shows MSC8101
external signals organized by function. Figure 1-2 indicates how the parallel input/output (I/O) ports signals are
multiplexed. Because the parallel I/O design supported by the MSC8101 communications processor module
(CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins are not numbered
sequentially.
Freescale Semiconductor
Power (V
Clock
Reset, configuration, and EOnCE
Memory Controller
CPM Input/Output Parallel Ports
JTAG Test Access Port
Reserved (denotes connections that are always reserved)
System bus, HDI16, and interrupts
CC
, V
DD
, and GND)
Functional Group
Table 1-1.
MSC8101 Technical Data, Rev. 19
MSC8101
Functional Signal Groupings
Port C
Port D
Port A
Port B
Number of Signal
Connections
133
80
11
27
26
14
18
6
8
5
5
Detailed Description
Table 1-10 on page 1-33
Table 1-11 on page 1-36
Table 1-12 on page 1-36
Table 1-6 on page 1-13
Table 1-7 on page 1-16
Table 1-8 on page 1-21
Table 1-9 on page 1-24
Table 1-2 on page 1-4
Table 1-3 on page 1-4
Table 1-4 on page 1-5
Table 1-5 on page 1-7
1
1-1

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