MSC8101ADS Freescale Semiconductor / Motorola, MSC8101ADS Datasheet - Page 54

• Manufacturer Part Number: MSC8101ADS
• Description: MSC8101 APP DEV SYSTEM
• Manufacturer: Freescale Semiconductor / Motorola

Physical and Electrical Specifications
2-14
Notes:
No.
31a
31b
31c
32a
32b
32c
33a
33b
35a
35b
34
No.
11g
11h
15a
15b
16
12
13
14
1
TA delay from the 50% level of the DLLIN rising edge
•
•
TEA delay from the 50% level of the DLLIN rising edge
•
•
PSDVAL delay from the 50% level of the DLLIN rising edge
•
•
Address bus delay from the 50% level of the DLLIN rising edge
•
•
Address attributes: TT/TBST/TSIZ/GBL delay from the 50% level of the DLLIN rising edge
BADDR delay from the 50% level of the DLLIN rising edge
Data bus delay from the 50% level of the DLLIN rising edge
•
•
DP delay from the 50% level of the DLLIN rising edge
•
•
Memory controller signals/ALE delay from the 50% level of the DLLIN rising edge
DBG/BR/DBB delay from the 50% level of the DLLIN rising edge
AACK/ABB/CS delay from the 50% level of the DLLIN rising edge
1.
2.
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
Multi master mode (SIUBCR[EBM] = 1)
Single master mode (SIUBCR[EBM] = 0)
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
TS set-up time before the 50% level of the DLLIN rising edge
BG set-up time before the 50% level of the DLLIN rising edge
Data bus set-up time before the 50% level of the DLLIN rising edge in Normal
•
•
Data bus set-up time before the 50% level of the DLLIN rising edge in ECC and PARITY modes
•
•
DP set-up time before the 50% level of the DLLIN rising edge
•
•
Address bus set-up time before the 50% level of the DLLIN rising edge
•
•
Address attributes: TT/TBST/TSIZ/GBL set-up time before the 50% level of the DLLIN rising edge
•
•
PUPMWAIT/IRQ signals set-up time before the 50% level of the DLLIN rising edge
The set-up time for these signals is for synchronous operation. Any set-up time can be used for asynchronous operation.
Input specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are
measured at the pin.
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
Pipeline mode
Non-pipeline mode
Extra cycle mode (SIUBCR[EXDD] = 0)
Non-extra cycle mode (SIUBCR[EXDD] = 1)
Extra cycle mode (SIUBCR[EXDD] = 0)
Non-extra cycle mode (SIUBCR[EXDD] = 1)
Characteristic
Table 2-17.
Table 2-16.
MSC8101 Technical Data, Rev. 19
Characteristic
AC Timing for SIU Outputs
AC Timing for SIU Inputs
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
30 pF
5.0
4.0
3.0
3.5
4.0
3.5
6.3
5.5
5.5
3.5
5.0
6.0
4.0
6.5
5.5
4.0
4.5
Maximum
Freescale Semiconductor
Value
50 pF
5.0
4.5
2.5
5.0
2.5
8.0
4.0
9.0
5.0
8.0
5.0
5.5
3.0
6.5
5.5
4.5
5.0
5.5
5.0
7.8
7.0
7.0
5.0
6.5
7.5
5.5
8.0
7.0
5.5
6.0
2
2
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns