MSC8101ADS Freescale Semiconductor / Motorola, MSC8101ADS Datasheet - Page 55

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MSC8101ADS

Manufacturer Part Number
MSC8101ADS
Description
MSC8101 APP DEV SYSTEM
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Freescale Semiconductor
Notes:
No.
35c
35d
36
BG delay from the 50% level of the DLLIN rising edge
TS delay from the 50% level of the DLLIN rising edge
Delay from the 50% level of the DLLIN rising edge for all other signals
1.
2.
The maximum bus frequency depends on the mode:
• In 60x-compatible mode connected to another MSC8101 device, the frequency is determined by adding the input and output
longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when
connected to another MSC8101 device, the frequency is determined by adding the input and output longest timing values,
which results in a frequency of 75 MHz for 30 pF output capacitance.
• Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in slower bus
frequencies.
• In single-master mode, the frequency depends on the timing of the devices connected to the MSC8101.
Output specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are
measured at the pin.
Characteristic
Table 2-17.
MSC8101 Technical Data, Rev. 19
AC Timing for SIU Outputs
Min.
1.0
1.0
1.0
30 pF
4.0
3.5
4.5
Maximum
50 pF
5.5
5.0
6.0
2
AC Timings
Units
ns
ns
ns
2-15

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