MSC8101ADS Freescale Semiconductor / Motorola, MSC8101ADS Datasheet - Page 51

• Manufacturer Part Number: MSC8101ADS
• Description: MSC8101 APP DEV SYSTEM
• Manufacturer: Freescale Semiconductor / Motorola

2.6.4.3 Host Reset Configuration
Host reset configuration allows the host to program the reset configuration word via the Host port after
deasserted, as described in the MSC8101 Reference Manual. The MSC8101 samples the signals described in Table
2-13 one the rising edge of
If HPE is sampled high, the host port is enabled. In this mode the
extends the internal
four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration word,
which is 32 bits wide. For more information, see the MSC8101 Reference Manual. The reset configuration word is
programmed before the internal PLL and DLL in the MSC8101 are locked. The host must program it after the
rising edge of the
MSC8101 clock. After the PLL and DLL are locked,
then released. The
2.6.4.4 Hardware Reset Configuration
Hardware reset configuration is enabled if
RSTCONF
RSTCONF
Freescale Semiconductor
Note:
No.
6
Delay from SPLL lock to SRESET deassertion
•
•
Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence.
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
DLL disabled
— BCLK = 18 MHz
— BCLK = 75 MHz
while
is deasserted (driven high) while
Output (I/O)
Output (I/O)
PORESET
PORESET
HRESET
SRESET
PORESET
Internal
PORESET
Input
SRESET
PORESET
asserted for
CLKIN.
min 16
changes from assertion to deassertion determines the MSC8101 configuration. If
1
PORESET
is released three bus clocks later (see Figure 2-7).
input. In this mode, the host must have its own clock that does not depend on the
Characteristics
until the host programs the reset configuration word register. The host must write
Figure 2-7.
Any time
Table 2-14.
RSTCONF, HPE
HRM, BTM
pins are sampled
when the signal is deasserted.
Reset Configuration
MSC8101 Technical Data, Rev. 19
Host programs
HPE
PORESET
2
Word
is sampled low at the rising edge of
Host Reset Configuration Timing
Reset Timing (Continued)
HRESET
changes, the MSC8101 acts as a configuration slave. If
PLL locked
PLL locks after
800 SPLLMFCLKs and
DLL locks 3073 BUS clocks
after PLL is locked.
When DLL is disabled,
reset period is shortened by
DLL lock time.
MODCK[1–3] pins
are sampled.
MODCK_H bits
are ready for PLL.
3
remains asserted for another 512 bus clocks and is
RSTCONF
DLL locked
Expression
3588 / BLCK
515 / BLCK
4
pin must be pulled up. The device
HRESET/SRESET are
extended for 512/515 BUS
clocks, respectively, from PLL
and DLL lock
PORESET
5
6
Min
. The value driven on
199.33
47.84
28.61
6.87
Max
PORESET
AC Timings
Unit
μs
μs
μs
μs
2-11
is