ST72345C4 STMicroelectronics, ST72345C4 Datasheet - Page 51

• Manufacturer Part Number: ST72345C4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72345C4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
7.6.5
Register description
System integrity (SI) control/status register (SICSR)
Reset value: 000x 000x (xxh)
Bit 7 = Reserved, must be kept cleared.
Bit 6 = AVDIE Voltage detector interrupt enable
Bit 5 = AVDF Voltage Detector flag
Bit 4 = LVDRF LVD reset flag
Bit 3 = LOCKED PLL Locked Flag
Bits 2:1 = Reserved, must be kept cleared.
Bit 0 = WDGRF Watchdog reset flag
Table 12.
This bit is set and cleared by software. It enables an interrupt to be generated when the
AVDF flag goes from 0 to 1. The pending interrupt information is automatically cleared
when software enters the AVD interrupt routine.
0: PDVD interrupt disabled
1: PDVD interrupt enabled
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt
request is generated when the AVDF bit goes from 0 to 1. Refer to
Section 7.6.2
0: V
1: V
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag
description for more details. When the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
This bit is set and cleared by hardware. It is set automatically when the PLL reaches its
operating frequency.
0: PLL not locked
1: PLL locked
This bit indicates that the last Reset was generated by the Watchdog peripheral. It is
set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD
Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF flag information, the flag description is given by the following
table.
7
0
DD
DD
over V
under V
LVDRF and WDGRF description
PDVDIE
IT+(AVD)
for additional details.
External RESET pin
IT-(AVD)
Reset sources
Watchdog
LVD
threshold
threshold
AVDF
Doc ID 12321 Rev 5
LVDRF
Read/Write
LOCKED
Supply, reset and clock management
LVDRF
0
0
0
1
Figure 19
0
WDGRF
WDGRF
X
and to
0
1
0
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