ST72345C4 STMicroelectronics, ST72345C4 Datasheet - Page 33

• Manufacturer Part Number: ST72345C4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72345C4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Note:
5.4
5.4.1
5.4.2
5.4.3
5.5
Figure 9.
If a programming cycle is interrupted (by reset action), the integrity of the data in memory
will not be guaranteed.
Power saving modes
Wait mode
The data EEPROM can enter Wait mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters Active Halt mode.The data EEPROM will
immediately enter this mode if there is no programming in progress, otherwise the data
EEPROM will finish the cycle and then enter Wait mode.
Active-halt mode
Refer to Wait mode.
Halt mode
The data EEPROM immediately enters Halt mode if the microcontroller executes the Halt
instruction. Therefore the EEPROM will stop the function in progress, and data may be
corrupted.
Access error handling
If a read access occurs while E2LAT = 1, then the data bus will not be driven.
If a write access occurs while E2LAT = 0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by reset action), the integrity of the data in memory
will not be guaranteed.
E2PGM bit
E2LAT bit
definition
Row
Data EEPROM write operation
Byte 1 Byte 2
⇓ Row / Byte ⇒ 0 1 2 3
Set by USER application
Writing data latches
...
N
0
1
PHASE 1
Read operation impossible
Doc ID 12321 Rev 5
Byte 32
Waiting E2PGM and E2LAT to fall
Programming cycle
PHASE 2
...
30 31
Nx20h...Nx20h+1Fh
Physical address
Read operation possible
00h...1Fh
20h...3Fh
Cleared by hardware
Data EEPROM
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