ST72345C4 STMicroelectronics, ST72345C4 Datasheet - Page 124

• Manufacturer Part Number: ST72345C4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72345C4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
11.4.6
Note:
Caution:
124/247
Figure 62. Single master / multiple slave configuration
Low-power modes
Table 52.
Using the SPI to wake up the device from Halt mode
In slave configuration, the SPI is able to wake up the device from Halt mode through a SPIF
interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
The SPI can wake up the device from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the device enters Halt mode. So, if
Slave selection is configured as external (see
master drives a low level on the SS pin when the slave enters Halt mode.
Mode
Wait
Halt
5V
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the device is woken up by
an interrupt with “exit from Halt mode” capability. The data received is subsequently read
from the SPIDR register when the software is running (interrupt vector fetching). If several
data are received before the wake-up event, then an overrun error is generated. This error
can be detected after the fetch of the interrupt routine that woke up the Device.
MOSI
Description
SCK
SS
SCK
MOSI
Master
Device
Device
Slave
MISO
MISO
SS
Doc ID 12321 Rev 5
MOSI
SCK
Device
Slave
MISO
SS
Description
Slave select
MOSI
SCK
Device
Slave
management), make sure the
MISO
SS
ST72344xx ST72345xx
MOSI
SCK
Device
Slave
MISO
SS