ST72345C4 STMicroelectronics, ST72345C4 Datasheet - Page 142

• Manufacturer Part Number: ST72345C4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72345C4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
11.5.6
11.5.7
Note:
Note:
142/247
Interrupts
Table 58.
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
Register description
Status register (SCISR)
Reset value: 1100 0000 (C0h)
Bit 7 = TDRE Transmit data register empty.
Data is not transferred to the shift register until the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
TC is not set after the transmission of a Preamble or a Break.
Bit 5 = RDRF Received data ready flag.
Transmit data register empty
Transmission complete
Received data ready to be read
Overrun error detected
Idle line detected
Parity error
TDRE
This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register.
It is cleared by a software sequence (an access to the SCISR register followed by a
write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
This bit is set by hardware when transmission of a frame containing Data is complete.
An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a write to the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
This bit is set by hardware when the content of the RDR register has been transferred
to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is
7
Interrupt event
Interrupt events
TC
RDRF
Doc ID 12321 Rev 5
TDRE
TC
RDRF
OR
IDLE
PE
Event flag
IDLE
Read-only
OR
TIE
TCIE
RIE
ILIE
PIE
Enable control
bit
NF
Yes
ST72344xx ST72345xx
Exit from
Wait
FE
No
Exit from
Halt
PE
0