ST72345C4 STMicroelectronics, ST72345C4 Datasheet - Page 128

• Manufacturer Part Number: ST72345C4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72345C4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
128/247
SPI data I/O register (SPIDR)
Reset value: Undefined
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see
Table 55.
7
0021h
0022h
0023h
Address
(Hex.)
D7
Warning:
SPIDR
Reset value
SPICR
Reset value
SPICSR
Reset value
Register
SPI register map and reset values
label
D6
A write to the SPIDR register places data directly into the
shift register for transmission.
Figure
MSB
x
SPIE
0
SPIF
0
7
D5
56).
Doc ID 12321 Rev 5
x
SPE
0
WCOL
0
6
D4
x
SPR2
0
OR
0
Read/Write
5
MODF
MSTR
D3
4
0
0
x
CPOL
3
0
x
x
D2
CPHA
ST72344xx ST72345xx
SOD
2
0
x
x
D1
SPR1
SSM
1
0
x
x
0
SPR0
D0
LSB
SSI
0
x
x
0