ST72345C4 STMicroelectronics, ST72345C4 Datasheet - Page 182

• Manufacturer Part Number: ST72345C4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72345C4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
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I2C slave 1 address register (I2C3SSAR1)
Reset value: 0000 0000 (00h)
Bits 7:1 = ADDR[7:1] Address of Slave 1
Bit 0= EN1 Enable bit for Slave Address 1
I2C slave 2 address register (I2C3SSAR2)
Reset value: 0000 0000 (00h)
Bits 7:1 = ADDR[7:1] Address of Slave 2.
Bit 0= EN2 Enable bit for Slave Address 2
I2C slave 3 address register (I2C3SSAR3)
Reset value: 0000 0000 (00h)
Bit 7:1 = ADDR[7:1] Address of Slave 3
Bit 0= EN3 Enable bit for Slave Address 3
7
ADDR7
ADDR7
ADDR7
This register contains the first 7 bits of Slave 1 address (excluding the LSB) and is user
programmable. It is also cleared by hardware when interface is disabled (PE =0).
This bit is used to enable/disable Slave Address 1. It is also cleared by hardware when
interface is disabled (PE =0).
0: Slave Address 1 disabled
1: Slave Address 1 enabled
This register contains the first 7 bits of Slave 2 address (excluding the LSB) and is user
programmable. It is also cleared by hardware when interface is disabled (PE =0).
This bit is used to enable/disable Slave Address 2. It is also cleared by hardware when
interface is disabled (PE =0).
0: Slave Address 2 disabled
1: Slave Address 2 enabled
This register contains the first 7 bits of Slave 3 address (excluding the LSB) and is user
programmable. It is also cleared by hardware when interface is disabled (PE =0).
This bit is used to enable/disable Slave Address 3. It is also cleared by hardware when
interface is disabled (PE =0).
0: Slave Address 3 disabled
1: Slave Address 3 enabled
7
7
ADDR6
ADDR6
ADDR6
ADDR5
ADDR5
ADDR5
Doc ID 12321 Rev 5
ADDR4
ADDR4
ADDR4
Read / Write
Read / Write
Read / Write
ADDR3
ADDR3
ADDR3
ADDR2
ADDR2
ADDR2
ST72344xx ST72345xx
ADDR1
ADDR1
ADDR1
0
EN1
EN2
EN3
0
0