ST72345C4 STMicroelectronics, ST72345C4 Datasheet - Page 117

• Manufacturer Part Number: ST72345C4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72345C4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Figure 57. Single master/ single slave application
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
●
●
In Master mode:
–
In Slave Mode:
There are two cases depending on the data/clock timing relationship (see
If CPHA = 1 (data latched on second clock edge):
–
If CPHA = 0 (data latched on first clock edge):
–
MSBit
GENERATOR
8-bit SHIFT REGISTER
SS internal must be held high continuously
SS internal must be held low during the entire transmission. This implies that in
single slave applications the SS pin either can be tied to V
standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in
the in the SPICSR register)
SS internal must be held low during byte transmission and pulled high between
each byte to allow the slave to write to the shift register. If SS is not pulled high, a
Write Collision error will occur when the slave writes to the shift register (see
collision error (WCOL) on page
CLOCK
SPI
MASTER
LSBit
Figure
Doc ID 12321 Rev 5
59).
MOSI
SCK
SS
MISO
122).
+5V
MISO
MOSI
SCK
SS
MSBit
Not used if SS is managed
by software
8-bit SHIFT REGISTER
SS
On-chip peripherals
, or made free for
SLAVE
Figure
LSBit
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Write
58):