ST72345C4 STMicroelectronics, ST72345C4 Datasheet - Page 42

• Manufacturer Part Number: ST72345C4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72345C4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

Supply, reset and clock management
7.2
Caution:
Caution:
42/247
Phase locked loop
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external
clock by 4 or 8 to obtain f
of 4 or 8 is selected by 3 option bits. Refer to
the required frequency and the application voltage. Refer to
description.
Table 7.
1. For a target ratio of x4 between 3.3 V - 3.65 V, this is the recommended configuration.
Figure 14. PLL output frequency timing diagram
When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs
the clock after a delay of t
When the PLL output signal reaches the operating frequency, the LOCKED bit in the
SICSCR register is set. Full PLL accuracy (ACC
t
Refer to
The PLL is not recommended for applications where timing accuracy is required.
When the RC oscillator and the PLL are enabled, it is recommended to calibrate this clock
through the RCCRH and RCCRL registers.
STAB
(see
Target ratio
Section 7.6.5 on page 51
Figure
x4
x4
x8
PLL configurations
(1)
14).
4/8 x
input
freq.
OSC
STARTUP
t
STARTUP
of 4 or 8 MHz. The PLL is enabled and the multiplication factor
Doc ID 12321 Rev 5
2.7 V - 3.65 V
.
3.3 V - 5.5 V
for a description of the LOCKED bit in the SICSR register.
t
LOCK
V
DD
Table 7
LOCKED bit set
PLL
t
STAB
) is reached after a stabilization time of
for the PLL configuration depending on
PLL ratio
Section 15.1
x4
x8
x8
t
ST72344xx ST72345xx
for the option byte
DIV2
OFF
OFF
ON