SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 649

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

33. Analog-to-digital Converter (ADC)
33.1
33.2
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Description
Embedded Characteristics
The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Control-
ler. Refer to the Block Diagram:
making possible the analog-to-digital conversions of 16 analog lines. The conversions extend
from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion
results are reported in a common register for all channels, as well as in a channel-dedicated reg-
ister. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from
Timer Counter output(s) are configurable.
The comparison circuitry allows automatic detection of values below a threshold, higher than a
threshold, in a given range or outside the range, thresholds and ranges being fully configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC
channel. These features reduce both power consumption and processor intervention.
age node that may be equal to the analog supply voltage. An external decoupling capacitance is
required for noise filtering.
Finally, the user can configure ADC timings, such as Startup Time and Tracking Time.
A whole set of reference voltages is generated internally from a single external reference volt-
• 10-bit Resolution
• 500 kHz Conversion Rate
• Wide Range Power Supply Operation
• Integrated Multiplexer Offering Up to 16 Independent Analog Inputs
• Individual Enable and Disable of Each Channel
• Hardware or Software Trigger
• PDC Support
• Possibility of ADC Timings Configuration
• Two Sleep Modes and Conversion Sequencer
• Standby Mode for Fast Wakeup Time Response
• Automatic Window Comparison of Converted Values
• Write Protect Registers
– External Trigger Pin
– Timer Counter Outputs (Corresponding TIOA Trigger)
– Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all
– Possibility of Customized Channel Sequence
– Power Down Capability
Enabled Channels
Figure
33-1. It also integrates a 16-to-1 analog multiplexer,
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