SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 531

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

Figure 30-4. Fractional Baud Rate Generator
30.7.1.3
30.7.1.4
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
SCK
Reserved
MCK/DIV
MCK
Baud Rate in Synchronous Mode or SPI Mode
Baud Rate in ISO 7816 Mode
USCLKS
0
1
2
3
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 3 times lower than the
system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the receive part
limits the SCK maximum frequency to MCK/3 in USART mode, or MCK/6 in SPI mode.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the
value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the
SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty
cycle on the SCK pin, even if the value programmed in CD is odd.
The ISO7816 specification defines the bit rate with the following formula:
Baudrate
BaudRate
16-bit Counter
CD
=
B
---------------------------------------------------------------- -
⎛
⎝
8 2 Over
Modulus
=
Control
=
(
FP
SelectedClock
------------------------------------- -
Di
----- -
Fi
SelectedClock
–
×
CD
f
) CD
⎛
⎝
glitch-free
USCLKS = 3
+
FP
------ -
logic
FP
8
⎞
⎠
⎞
⎠
SYNC
0
CD
>1
1
0
1
0
OVER
Sampling
Divider
FIDI
0
1
SYNC
SCK
SAM3N
SAM3N
Baud Rate
Sampling
Clock
Clock
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