SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 550

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

30.7.7
30.7.7.1
30.7.7.2
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
SPI Mode
Modes of Operation
Baud Rate
The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides com-
munication with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master” which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turns being masters and one master may simultaneously shift data into
multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where one
CPU is always the master while all of the others are always slaves.) However, only one slave
may drive its output to write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI
Master mode can address only one SPI Slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
The USART can operate in SPI Master Mode or in SPI Slave Mode.
Operation in SPI Master Mode is programmed by writing to 0xE the USART_MODE field in the
Mode Register. In this case the SPI lines must be connected as described below:
Operation in SPI Slave Mode is programmed by writing to 0xF the USART_MODE field in the
Mode Register. In this case the SPI lines must be connected as described below:
In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a soft-
ware reset of the transmitter and of the receiver (except the initial configuration after a hardware
reset). (See
In SPI Mode, the baudrate generator operates in the same way as in USART synchronous
mode:
some restrictions:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input
• Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data
• Slave Select (NSS): This control line allows the master to select or deselect the slave.
• the MOSI line is driven by the output pin TXD
• the MISO line drives the input pin RXD
• the SCK line is driven by the output pin SCK
• the NSS line is driven by the output pin RTS
• the MOSI line drives the input pin RXD
• the MISO line is driven by the output pin TXD
• the SCK line drives the input pin SCK
• the NSS line drives the input pin CTS
into the input of the slave.
of the master.
bits. The master may transmit data at a variety of baud rates. The SCK line cycles once for
each bit that is transmitted.
See “Baud Rate in Synchronous Mode or SPI Mode” on page 531.
Section
30.7.7.4).
However, there are
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