SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 392

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

Figure 26-5. Input Glitch Filter Timing
392
392
SAM3N
SAM3N
if PIO_IFSR = 0
if PIO_IFSR = 1
PIO_PDSR
PIO_PDSR
Pin Level
MCK
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV
field of the PIO_SCDR (Slow Clock Divider Register)
Tdiv_slclk = ((DIV+1)*2).Tslow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2
Selected Clock Cycle (Selected Clock represents MCK or Divided Slow Clock depending on
PIO_IFSCDR and PIO_IFSCER programming) is automatically rejected, while a pulse with a
duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is accepted. For pulse
durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may
not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to
be visible it must exceed 1 Selected Clock cycle, whereas for a glitch to be reliably filtered out,
its duration must not exceed 1/2 Selected Clock cycle.
The filters also introduce some latencies, this is illustrated in
The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs
on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt
detection. The glitch and debouncing filters require that the PIO Controller clock is enabled.
• If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2
Period of the Programmable Divided Slow Clock.
1 cycle
1 cycle
PIO_IFCSR = 0
up to 1.5 cycles
1 cycle
up to 2.5 cycles
2 cycles
Figure 26-5
up to 2 cycles
and
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
1 cycle
1 cycle
Figure
26-6.