SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 182

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

10.21.11.1
Memory Management Fault Status Register
The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are:
7
6
5
4
3
2
1
0
MMARVALID
Reserved
MSTKERR
Reserved
DACCVIOL
IACCVIOL
MUNSTKERR
• MMARVALID
Memory Management Fault Address Register (MMAR) valid flag:
0 = value in MMAR is not a valid fault address
1 = MMAR holds a valid fault address.
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set
this bit to 0. This prevents problems on return to a stacked active memory management fault handler whose MMAR value
has been overwritten.
• MSTKERR
Memory manager fault on stacking for exception entry:
0 = no stacking fault
1 = stacking for an exception entry has caused one or more access violations.
When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor
has not written a fault address to the MMAR.
• MUNSTKERR
Memory manager fault on unstacking for a return from exception:
0 = no unstacking fault
1 = unstack for an exception return has caused one or more access violations.
This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The proces-
sor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a
fault address to the MMAR.
• DACCVIOL
Data access violation flag:
0 = no data access violation fault
1 = the processor attempted a load or store at a location that does not permit the operation.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has loaded
the MMAR with the address of the attempted access.
• IACCVIOL
Instruction access violation flag:
0 = no instruction access violation fault
1 = the processor attempted an instruction fetch from a location that does not permit execution.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not
written a fault address to the MMAR.
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11011A–ATARM–04-Oct-10