SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 153

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

10.20.2
• SETENA
Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, assert-
ing its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its
priority.
11011A–ATARM–04-Oct-10
31
23
15
7
Interrupt Set-enable Registers
30
22
14
6
The ISER0 register enables interrupts, and show which interrupts are enabled. See:
The bit assignments are:
• the register summary in
•
Table 10-28 on page 152
29
21
13
5
28
20
12
4
Table 10-27 on page 151
SETENA bits
SETENA bits
SETENA bits
SETENA bits
for which interrupts are controlled by each register.
27
19
11
3
for the register attributes
26
18
10
2
25
17
9
1
SAM3N
24
16
8
0
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