MCP3901A0T-E/ML Microchip Technology, MCP3901A0T-E/ML Datasheet - Page 48

• Manufacturer Part Number: MCP3901A0T-E/ML
• Description: IC AFE 24BIT 64KSPS 2CH 20QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3901A0T-E/ML

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3901
7.6
The Configuration registers contain settings for the
internal clock prescaler, the oversampling ratio, the
Channel 0 and Channel 1 width settings of 16 or
REGISTER 7-6:
DS22192D-page 48
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13-12
bit 11-10
bit 9-8
bit 7-6
bit 5-4
bit 3-2
PRESCALE
RESET
R/W-0
R/W-0
_CH1
<1>
Configuration Registers
PRESCALE<1:0>: Internal Master Clock (AMCLK) Prescaler Value bits
11 = AMCLK = MCLK/8
10 = AMCLK = MCLK/4
01 = AMCLK = MCLK/2
00 = AMCLK = MCLK (default)
OSR<1:0>: Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, DMCLK/DRCLK)
11 = 256
10 = 128
01 = 64 (default)
00 = 32
WIDTH_CH<1:0>: ADC Channel Output Data Word Width bits
1 = 24-bit mode
0 = 16-bit mode (default)
MODOUT_CH<1:0>: Modulator Output Setting for MDAT Pins bits
11 = Both CH0 and CH1 modulator outputs present on MDAT1 and MDAT0 pins
10 = CH1 ADC modulator output present on MDAT1 pin
01 = CH0 ADC modulator output present on MDAT0 pin
00 = No modulator output is enabled (default)
RESET_CH<1:0>: Reset Mode Setting for ADCs bits
11 = Both CH0 and CH1 ADC are in Reset mode
10 = CH1 ADC in Reset mode
01 = CH0 ADC in Reset mode
00 = Neither Channel in Reset mode (default)
SHUTDOWN_CH<1:0>: Shutdown Mode Setting for ADCs bits
11 = Both CH0 and CH1 ADC are in Shutdown
10 = CH1ADC is in shutdown
01 = CH0 ADC is in shutdown
00 = Neither Channel is in shutdown (default)
DITHER_CH<1:0>: Control for Dithering Circuit bits
11 = Both CH0 and CH1 ADC have dithering circuit applied (default)
10 = Only CH1 ADC has dithering circuit applied
01 = Only CH0 ADC has dithering circuit applied
00 = Neither Channel has dithering circuit applied
PRESCALE
RESET
R/W-0
R/W-0
_CH0
<0>
CONFIGURATION REGISTERS:
CONFIG1: ADDRESS 0x0A, CONFIG2: ADDRESS 0x0B
W = Writable bit
‘1’ = Bit is set
SHUTDOWN
OSR<1>
R/W-0
R/W-0
_CH1
SHUTDOWN
OSR<0>
R/W-1
R/W-0
_CH0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
24 bits, the modulator output control settings, the state
of the channel Resets and shutdowns, the dithering
algorithm control (for Idle tones suppression), and the
control bits for the external V
DITHER
WIDTH
R/W-0
R/W-1
_CH1
_CH1
DITHER
WIDTH
R/W-0
R/W-1
_CH0
_CH0
© 2011 Microchip Technology Inc.
x = Bit is unknown
VREFEXT
MODOUT
REF
R/W-0
R/W-0
_CH1
and external CLK.
MODOUT
CLKEXT
R/W-0
R/W-0
_CH0
bit 8
bit 0