MCP3901A0T-E/ML Microchip Technology, MCP3901A0T-E/ML Datasheet - Page 33

• Manufacturer Part Number: MCP3901A0T-E/ML
• Description: IC AFE 24BIT 64KSPS 2CH 20QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3901A0T-E/ML

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.0
6.1
The MCP3901 device is compatible with SPI Modes 0,0
and 1,1. Data is clocked out of the MCP3901 on the
falling edge of SCK and data is clocked into the
MCP3901 on the rising edge of SCK. In these modes,
SCK can Idle either high or low.
Each SPI communication starts with a CS falling edge
and stops with the CS rising edge. Each SPI
communication is independent. When CS is high, SDO
is in high-impedance, and transitions on SCK and SDI
have no effect. Additional controls: RESET, DR and
MDAT0/1 are also provided on separate pins for
advanced communication.
The MCP3901 interface has a simple command
structure. The first byte transmitted is always the
CONTROL byte and is followed by data bytes that are
8-bit wide. Both ADCs are continuously converting data
by default and can be reset or shut down through a
CONFIG2 register setting.
Since each ADC data is either 16 or 24 bits (depending
on the WIDTH bits), the internal registers can be
grouped together with various configurations (through
the READ bits) in order to allow easy data retrieval within
only one communication. For device reads, the internal
address counter can be automatically incremented in
order to loop through groups of data within the register
map. The SDO will then output the data located at the
ADDRESS (A<4:0>) defined in the control byte and then
ADDRESS + 1 depending on the READ<1:0> bits,
which select the groups of registers. These groups are
defined in
Registers”
The Data Ready pin (DR) can be used as an interrupt
for an MCU and outputs pulses when new ADC
channel data is available. The RESET pin acts like a
Hard Reset and can reset the part to its default power-
up configuration. The MDAT0/1 pins give the modulator
outputs (see
6.2
The control byte of the MCP3901 contains two device
Address bits, A<6:5>, 5 register Address bits, A<4:0>,
and a Read/Write bit (R/W). The first byte transmitted
to the MCP3901 is always the control byte.
The MCP3901 interface is device addressable
(through A<6:5>) so that multiple MCP3901 chips can
be present on the same SPI bus with no data bus
contention. This functionality enables three-phase
power metering systems, containing three MCP3901
chips, controlled by a single SPI bus (single CS, SCK,
SDI and SDO pins).
© 2011 Microchip Technology Inc.
SERIAL INTERFACE
DESCRIPTION
Overview
Control Byte
Section 7.1 “ADC Channel Data Output
(Register Map).
Section 5.4 “Modulator Output
Block”).
FIGURE 6-1:
The default device address bits are ‘00’. Contact the
Microchip factory for additional device address bits. For
more information, please see the
System
A read on undefined addresses will give an all zeros
output on the first, and all subsequent transmitted
bytes. A write on an undefined address will have no
effect and also, will not increment the address counter.
The register map is defined in
Channel Data Output
6.3
The first data byte read is the one defined by the
address given in the CONTROL byte. After this first
byte is transmitted, if the CS pin is maintained low, the
communication continues and the address of the next
transmitted byte is determined by the status of the
READ bits in the STATUS/COM register. Multiple
looping configurations can be defined through the
READ<1:0> bits for the address increment (see
Section 6.6 “SPI MODE 0,0 – Clock Idle Low, Read/
Write
6.4
The first data byte written is the one defined by the
address given in the control byte. The write
communication automatically increments the address
for subsequent bytes.
The address of the next transmitted byte within the
same communication (CS stays low) is the next
address defined on the register map. At the end of the
register map, the address loops to the beginning of the
register map. Writing a non-writable register has no
effect.
The SDO pin stays in high-impedance during a write
communication.
6.5
In this SPI mode, the clock Idles high. For the
MCP3901, this means that there will be a falling edge
before there is a rising edge.
Note:
A6
Address
Examples”).
Device
Bits
section.
Writing to the Device
SPI MODE 1,1 – Clock Idle High,
Read/Write Examples
Reading from the Device
A5 A4
Changing from an SPI Mode 1,1 to an SPI
Mode 0,0 is possible, but needs a Reset
pulse in-between to ensure correct
communication.
A3 A2
Address Bits
Control Byte.
Registers”.
Register
MCP3901
A1
Product Identification
Section 7.1 “ADC
DS22192D-page 33
A0
Write Bit
R/W
Read/