MCP3901A0T-E/ML Microchip Technology, MCP3901A0T-E/ML Datasheet - Page 31

• Manufacturer Part Number: MCP3901A0T-E/ML
• Description: IC AFE 24BIT 64KSPS 2CH 20QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3901A0T-E/ML

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.10.1
The phase delay can only go from -OSR/2 to
+OSR/2 – 1. This sets the fine phase resolution. The
PHASE register is coded with two’s complement.
If larger delays between the two channels are needed,
they can be implemented externally to the chip with an
MCU. A FIFO in the MCU can save incoming data from
the leading channel for a number N of DRCLK clocks.
In this case, DRCLK would represent the coarse timing
resolution, and DMCLK, the fine timing resolution. The
total delay will then be equal to:
The Phase Delay register can be programmed once
with the OSR = 256 setting and will adjust to the OSR
automatically afterwards, without the need to change
the value of the PHASE register.
• OSR = 256: The delay can go from -128 to +127.
• OSR = 128: The delay can go from -64 to +63.
• OSR = 64: The delay can go from -32 to +31.
• OSR = 32: The delay can go from -16 to +15.
TABLE 5-8:
© 2011 Microchip Technology Inc.
0 1 1 1 1 1 1 1
0 1 1 1 1 1 1 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
Register Value
PHASE<7> is the sign bit, PHASE<6> is the MSB
and PHASE<0> is the LSB.
PHASE<6> is the sign bit, PHASE<5> is the MSB
and PHASE<0> is the LSB.
PHASE<5> is the sign bit, PHASE<4> is the MSB
and PHASE<0> is the LSB.
PHASE<4> is the sign bit, PHASE<3> is the MSB
and PHASE<0> is the LSB.
Delay = N/DRCLK + PHASE/DMCLK
PHASE
PHASE DELAY LIMITS
PHASE VALUES WITH
MCLK = 4 MHZ, OSR = 256
0x7F
0x7E
0xFF
0x01
0x00
0x81
0x80
Hex
(CH0 relative
to CH1)
+127 µs
+126 µs
-127 µs
-128 µs
Delay
+1 µs
-1 µs
0 µs
5.11
The MCP3901 includes a Pierce-type crystal oscillator
with very high stability and ensures very low
temperature and jitter for the clock generation. This
oscillator can handle up to 16.384 MHz crystal
frequencies provided that proper load capacitances
and the quartz quality factor are used.
For keeping specified ADC accuracy, AMCLK should
be kept between 1 and 5 MHz with BOOST off or 1 and
8.192 MHz with BOOST on. Larger MCLK frequencies
can be used provided the prescaler clock settings allow
the AMCLK to respect these ranges.
For a proper start-up, the load capacitors of the crystal
should be connected between OSC1 and DGND, and
between OSC2 and DGND. They should also respect
the following equation:
EQUATION 5-6:
When CLKEXT = 1, the crystal oscillator is bypassed
by a digital buffer to allow direct clock input for an
external clock (see
Where:
C
LOAD
R
M
f
Crystal Oscillator
R
M
=
=
=
<
1.6 10
Figure
Crystal frequency in MHz
Load capacitance in pF including
parasitics from the PCB
Motional resistance in ohms of
the quartz
×
6
1-5).
×
⎛
⎝
MCP3901
------------------------ -
f
×
C
1
LOAD
DS22192D-page 31
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