MCP3901A0T-E/ML Microchip Technology, MCP3901A0T-E/ML Datasheet - Page 37

• Manufacturer Part Number: MCP3901A0T-E/ML
• Description: IC AFE 24BIT 64KSPS 2CH 20QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3901A0T-E/ML

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.7.1
Both ADCs are powered up with their default
configurations, and begin to output DR pulses
immediately (RESET<1:0> and SHUTDOWN<1:0>
bits are off by default).
The default output codes for both ADCs are all zeros.
The default modulator output for both ADCs is ‘0011’
(corresponding to a theoretical zero voltage at the
inputs). The default phase is zero between the two
channels.
It is recommended to enter into ADC Reset mode for
both ADCs, just after power-up, because the desired
MCP3901 register configuration may not be the default
one, and in this case, the ADC would output undesired
data. Within the ADC Reset mode (RESET<1:0> = 11),
the user can configure the whole part with a single
communication. The write commands automatically
increment the address so that the user can start writing
the PHASE register and finish with the CONFIG2
register in only one communication (see
The RESET<1:0> bits are in the CONFIG2 register to
allow exiting the Soft Reset mode, and have the whole
part configured and ready to run in only one command.
The following register sets are defined as groups:
TABLE 6-1:
FIGURE 6-7:
© 2011 Microchip Technology Inc.
ADC DATA CH0
ADC DATA CH1
MOD, PHASE, GAIN
CONFIG, STATUS
AV
CS
SCK
SDI
DD
Group
CONFIG2 ADDR/W
CONTINUOUS WRITE
Optional Reset of Both ADCs
00011000
REGISTER GROUPS
Recommended Configuration Sequence at Power-up.
11XXXXXX
CONFIG2
Addresses
0x09-0x0B
0x00-0x02
0x03-0x05
0x06-0x08
PHASE ADDR/W
Figure
00001110
6-7).
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PHASE
One Command for Writing Complete Configuration
The following register sets are defined as types:
TABLE 6-2:
6.8
Immediately after the following actions, the ADCs are
temporarily reset in order to provide proper operation:
1.
2.
3.
4.
5.
After these temporary Resets, the ADCs go back to the
normal operation with no need for an additional
command. These are also the settings where the DR
position is affected. The PHASE register can be used
to serially Soft Reset the ADCs, without using the
RESET bits in the Configuration register, if the same
value is written in the PHASE register.
ADC DATA
(both channels)
CONFIGURATION
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Change in PHASE register.
Change in the OSR setting.
Change in the PRESCALE setting.
Overwrite of the same PHASE register value.
Change in the CLKEXT bit in the CONFIG2
register, modifying internal oscillator state.
GAIN
Situations that Reset ADC Data
Type
STATUS/COM
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REGISTER TYPES
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CONFIG1
MCP3901
Addresses
0x06-0x0B
0x00-0x05
DS22192D-page 37
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CONFIG2