MCP3901A0T-E/ML Microchip Technology, MCP3901A0T-E/ML Datasheet - Page 27

• Manufacturer Part Number: MCP3901A0T-E/ML
• Description: IC AFE 24BIT 64KSPS 2CH 20QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3901A0T-E/ML

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.5
Both ADCs present in the MCP3901 include a
decimation filter that is a third-order sinc (or notch)
filter. This filter processes the multi-bit bitstream into
16 or 24-bit words (depending on the WIDTH
Configuration bit). The settling time of the filter is
3 DMCLK periods. It is recommended that unsettled
data be discarded to avoid data corruption, which can
be done easily by setting the DR_LTY bit high in the
STATUS/COM register.
The resolution achievable at the output of the sinc filter
(the output of the ADC) is dependant on the OSR and
is summarized with the following table:
TABLE 5-3:
For 24-Bit Output mode (WIDTH = 1), the output of the
sinc filter is padded with least significant zeros for any
resolution less than 24 bits.
For 16-Bit Output modes, the output of the sinc filter is
rounded to the closest 16-bit number in order to
conserve only 16-bit words and to minimize truncation
error.
The gain of the transfer function of this filter is 1 at each
multiple of DMCLK (typically 1 MHz) so a proper
anti-aliasing filter must be placed at the inputs. This will
attenuate the frequency content around DMCLK and
keep the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple,
first-order RC network with a sufficiently low time
constant to generate high rejection at DMCLK
frequency.
EQUATION 5-1:
Where:
© 2011 Microchip Technology Inc.
OSR<1:0>
0
0
1
1
SINC
0
1
0
1
H z ( )
3
z
Filter
ADC RESOLUTION vs. OSR
=
=
OSR
128
256
exp
32
64
⎛
⎜
⎝
SINC FILTER TRANSFER
FUNCTION H(Z)
-------------------------------- -
OSR 1 z
⎛
⎝
1 z
--------------------- -
DMCLK
–
(
2πfj
–
ADC Resolution (bits)
OSR
–
No Missing Codes
1 –
⎞
⎠
)
⎞
⎟
⎠
3
17
20
23
24
The Normal Mode Rejection Ratio (NMRR) or gain of
the transfer function is given by the following equation:
EQUATION 5-2:
or:
where:
Figure 5-3
FIGURE 5-3:
MCLK = 4 MHz, OSR = 64, PRESCALE = 1.
-100
-120
-20
-40
-60
-80
20
0
1
NMRR f ( )
shows the sinc filter frequency response:
NMRR f ( )
10
sin
=
c x ( )
Input Frequency (Hz)
100
MAGNITUDE OF
FREQUENCY RESPONSE
H(f)
=
SINC Filter Response with
--------------------------------------------- -
sin
sin
=
c
---------------------------- -
c
sin
sin
⎛
⎝
⎛
⎝
1000
π
-------------- -
π
sin
c
c
⋅
MCP3901
⋅
⎛
⎝
⎛
⎝
x
--------------------- -
DMCLK
x ( )
--------------------
DRCLK
π
π
⋅
⋅
10000
---- -
f
--- -
f
f
f
f
f
D
S
⎞
⎠
⎞
⎠
DS22192D-page 27
3
⎞
⎠
⎞
⎠
100000 1000000
3