MCP3901A0T-E/ML Microchip Technology, MCP3901A0T-E/ML Datasheet - Page 19

• Manufacturer Part Number: MCP3901A0T-E/ML
• Description: IC AFE 24BIT 64KSPS 2CH 20QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3901A0T-E/ML

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
This section defines the terms and formulas used
throughout this data sheet. The following terms are
defined:
MCLK – Master Clock
AMCLK – Analog Master Clock
DMCLK – Digital Master Clock
DRCLK – Data Rate Clock
Oversampling Ratio (OSR)
Offset Error
Gain Error
Integral Nonlinearity Error
Signal-to-Noise Ratio (SNR)
Signal-to-Noise Ratio And Distortion (SINAD)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
MCP3901 Delta-Sigma Architecture
Idle Tones
Dithering
Crosstalk
PSRR
CMRR
ADC Reset Mode
Hardware Reset Mode (RESET = 0)
ADC Shutdown Mode
Full Shutdown Mode
4.1
This is the fastest clock present in the device. This is
the frequency of the crystal placed at the OSC1/OSC2
inputs when CLKEXT = 0 or the frequency of the clock
input at the OSC1/CLKI when CLKEXT = 1 (see
Figure
© 2011 Microchip Technology Inc.
1-5).
TERMINOLOGY AND
FORMULAS
MCLK – Master Clock
4.2
This is the clock frequency that is present on the analog
portion of the device, after prescaling has occurred via
the CONFIG1 PRESCALE<1:0> register bits. The
analog portion includes the PGAs and the two
Sigma-Delta modulators.
EQUATION 4-1:
TABLE 4-1:
4.3
This is the clock frequency that is present on the digital
portion of the device, after prescaling and division by 4.
This is also the sampling frequency, which is the rate
when the modulator outputs are refreshed. Each period
of this clock corresponds to one sample and one
modulator output (see
EQUATION 4-2:
4.4
This is the output data rate (i.e., the rate at which the
ADCs output new data). Each new data is signaled by
a Data Ready pulse on the DR pin.
This data rate is depending on the OSR and the
prescaler with the following formula:
EQUATION 4-3:
DRCLK
PRE<1:0>
0
0
1
1
Config
DMCLK
AMCLK – Analog Master Clock
DMCLK – Digital Master Clock
DRCLK – Data Rate Clock
=
DMCLK
--------------------- -
0
1
0
1
OSR
AMCLK
=
MCP3901 OVERSAMPLING
RATIO SETTINGS
AMCLK
-------------------- -
=
AMCLK = MCLK/1 (default)
AMCLK
---------------------
4
Figure
4
×
=
Analog Master Clock
OSR
AMCLK = MCLK/2
AMCLK = MCLK/4
AMCLK = MCLK/8
------------------------------ -
PRESCALE
=
MCLK
1-5).
MCP3901
=
--------------------------------------- -
4 PRESCALE
Prescale
×
---------------------------------------------------------- -
4
×
MCLK
OSR
DS22192D-page 19
MCLK
×
PRESCALE