MCP3901A0T-E/ML Microchip Technology, MCP3901A0T-E/ML Datasheet - Page 20

• Manufacturer Part Number: MCP3901A0T-E/ML
• Description: IC AFE 24BIT 64KSPS 2CH 20QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3901A0T-E/ML

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3901
Since this is the output data rate, and since the
decimation filter is a SINC (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
TABLE 4-2:
4.5
The ratio of the sampling frequency to the output data
rate is OSR = DMCLK/DRCLK. The default OSR is 64
or with MCLK = 4 MHz and PRESCALE = 1,
AMCLK = 4 MHz, f
following bits in the CONFIG1 register are used to
change the Oversampling Ratio (OSR).
TABLE 4-3:
DS22192D-page 20
Note:
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
OSR<1:0>
0
0
1
1
<1:0>
CONFIG
PRE
Oversampling Ratio (OSR)
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1.
0
1
0
1
OSR <1:0>
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE
MCP3901 OVERSAMPLING
RATIO SETTINGS
S
= 1 MHz, f
OVERSAMPLING RATIO
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OSR
256
128
256
128
256
128
256
128
64 (default)
64
32
64
32
64
32
64
32
D
OSR
128
256
= 15.625 ksps. The
32
AMCLK
MCLK/8
MCLK/8
MCLK/8
MCLK/8
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/2
MCLK/2
MCLK/2
MCLK
MCLK
MCLK
MCLK
MCLK/32
MCLK/32
MCLK/16
MCLK/16
MCLK/32
MCLK/32
MCLK/16
MCLK/16
DMCLK
MCLK/8
MCLK/8
MCLK/8
MCLK/8
MCLK/4
MCLK/4
MCLK/4
MCLK/4
The following table describes the various combinations
of OSR and PRESCALE, and their associated AMCLK,
DMCLK and DRCLK rates.
4.6
This is the error induced by the ADC when the inputs
are shorted together (V
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip
to chip. This offset error can easily be calibrated out by
a MCU with a subtraction. The offset is specified in mV.
The offset on the MCP3901 has a low temperature
coefficient; see
Curves”.
4.7
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in percent
(%) compared to the ideal transfer function defined by
Equation
and ADC gain error contributions, but not the V
contribution (it is measured with an external V
error varies with PGA and OSR settings.
The gain error on the MCP3901 has a low temperature
coefficient; see the typical performance curves for
more information,
MCLK/8192
MCLK/4096
MCLK/2048
MCLK/1024
MCLK/4096
MCLK/2048
MCLK/1024
MCLK/2048
MCLK/1024
MCLK/1024
MCLK/512
MCLK/512
MCLK/256
MCLK/512
MCLK/256
MCLK/128
DRCLK
Offset Error
Gain Error
5-3. The specification incorporates both PGA
Section 2.0 “Typical Performance
Figure 2-24
DRCLK
0.4882
7.8125
7.8125
15.625
7.8125
15.625
(ksps)
0.976
0.976
31.25
1.95
1.95
1.95
3.9
3.9
3.9
3.9
© 2011 Microchip Technology Inc.
IN
= 0V). The specification
and
SINAD
(dB)
91.4
86.6
78.7
68.2
91.4
86.6
78.7
68.2
91.4
86.6
78.7
68.2
91.4
86.6
78.7
68.2
Figure
2-25.
REF
ENOB
(bits)
14.89
14.10
12.78
11.04
14.89
14.10
12.78
11.04
14.89
14.10
12.78
11.04
14.89
14.10
12.78
11.04
). This
REF