MCP3901A0T-E/ML Microchip Technology, MCP3901A0T-E/ML Datasheet - Page 46

• Manufacturer Part Number: MCP3901A0T-E/ML
• Description: IC AFE 24BIT 64KSPS 2CH 20QFN
• Manufacturer: Microchip Technology
• Series: -r

Specifications of MCP3901A0T-E/ML

• Number Of Bits: 24
• Number Of Channels: 2
• Power (watts): -
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3901
7.5
This register contains all settings related to the
communication, including data ready settings and
status, and Read mode settings.
7.5.1
This bit determines if the first data ready pulses
correspond to settled data or unsettled data from each
SINC
every DRCLK period. If this bit is set, unsettled data will
wait for 3 DRCLK periods before giving DR pulses and
will then give DR pulses every DRCLK period.
7.5.2
This bit defines the non-active state of the data ready
pin (logic 1 or high-impedance). Using this bit, the user
can connect multiple chips with the same DR pin with a
pull-up resistor (DR_HIZN = 0) or a single chip with no
external component (DR_HIZN = 1).
7.5.3
If one of the channels is in Reset or shutdown, only one
of the data ready pulses is present and the situation is
similar to DRMODE = 01 or 10. In the ‘01’, ‘10’ and ‘11’
modes, the ADC channel data to be read is latched at
the beginning of a reading in order to prevent the case
of erroneous data when a DR pulse happens during a
read. In these modes, the two channels are
independent.
When these bits are equal to ‘11’,’10’ or ‘01’, they
control which ADC’s data ready is present on the DR
pin. When DRMODE = 00, the data ready pin output is
synchronized with the lagging ADC channel (defined by
the PHASE register) and the ADCs are linked together.
In this mode, the output of the two ADCs is latched
synchronously at the moment of the DR event. This
prevents bad synchronization between the two ADCs.
The output is also latched at the beginning of a reading
in order not to be updated during a read and not to give
erroneous data.
DS22192D-page 46
3
filter. Unsettled data will provide DR pulses
Status and Communication
Register
DATA READY (DR) LATENCY
CONTROL – DR_LTY
DATA READY (DR) PIN HIGH Z –
DR_HIZN
DATA READY MODE –
DRMODE<1:0>
This mode is very useful for power metering
applications because the data from both ADCs can be
retrieved, using this single data ready event, and
processed synchronously even in case of a large
phase difference. This mode works as if there was one
ADC channel and its data would be 48 bits long and
contain both channel data. As a consequence, if one
channel is in Reset or shutdown when DRMODE = 00,
no data ready pulse will be present at the outputs (if
both channels are not ready in this mode, the data is
not considered ready).
See
details about data ready pin behavior.
7.5.4
These bits indicate the DR status of both channels,
respectively. These flags are set to logic high after each
read of the STATUS/COM register. These bits are
cleared when a DR event has happened on its
respective ADC channel. Writing these bits has no
effect.
Note:
Section 6.9 “Data Ready Pin (DR)”
DR STATUS FLAG –
DRSTATUS<1:0>
These bits are useful if multiple devices
share
(DR_HIZN = 0), in order to understand
what DR event happened. This configura-
tion can be used for three-phase power
metering systems, where all three phases
share the same data ready pin. In case
the DRMODE = 00 (linked ADCs), these
data ready status bits will be updated syn-
chronously upon the same event (lagging
ADC is ready). These bits are also useful
in systems where the DR pin is not used
to save MCU I/O.
the
© 2011 Microchip Technology Inc.
same
DR
output
for more
pin