PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 428

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

13.6.5.2 Receive Cycle Timing
Figure 100
Note:
1. Whichever supplies the receive clock depending on the selected clock mode:
2. NRZ, NRZI and Manchester data encoding
3. FM0 and FM1 data encoding
4. If Carrier Detect auto start feature enabled (not for clock modes 1 and 5)
5. A receive clock must be present to detect input level changes of signal CD.
Data Sheet
externally clocked via RxCLK or XTAL1 or
internally clocked via DPLL, BRG or BCR.
(No edge relation can be measured if the internal receive clock is derived from the
external clock source by devision stages (BGR, BCR) or DPLL)
Receive Clock
(Note 1)
(Note 2)
(Note 3)
(Note 4)
Receive Cycle Timing
RxD
RxD
CD
91
93
92
428
91
91
90
94
92
92
Electrical Characteristics
PEB 20534
PEF 20534
2000-05-30