PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 412

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Figure 87
Table 115
Symbol
V
V
V
V
The timings below show the basic read and write transaction between an initiator
(Master) and a target (Slave) device. The DSCC4 is able to work both as master and
slave.
As a master the DSCC4 reads/writes data from/to host memory using DMA and burst.
The slave mode is used by an CPU to access the DSCC4 PCI Configuration Space, the
on-chip registers and to access peripherals connected to the DSCC4 Local Bus Interface
(LBI).
13.6.1.1 PCI Read Transaction
The transaction starts with an address phase which occurs during the first cycle when
FRAME is activated (clock 2 in
outputs a valid address on AD(31:0) and a valid bus command on C/BE(3:0). The first
clock of the first data phase is clock 3. During the data phase C/BE indicate which byte
lanes on AD(31:0) are involved in the current data phase.
The first data phase on a read transaction requires a turn-around cycle. In
address is valid on clock 2 and then the master stops driving AD. The target drives the
AD lines following the turnaround when DEVSEL is asserted. (TRDY cannot be driven
until DEVSEL is asserted.) The earliest the target can provide valid data is clock 4. Once
enabled, the AD output buffers of the target stay enabled through the end of the
transaction.
Data Sheet
th
tl
test
max
PCI Input Timing Measurement Waveforms
PCI Input and Output Measurement Conditions
Value
2.4
0.4
1.5
2.0
Figure
Unit
V
V
V
V
88). During this phase the bus master (initiator)
412
Electrical Characteristics
Figure 88
PEB 20534
PEF 20534
2000-05-30
the