PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 129

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

– Support of PPP Data Link Layer frame transmission
– FIFO buffers for efficient transfer of data packets
– High Data Rate (PEB 20534H-52 only)
Features included by each one of the SCCs:
• Serial Interface
• Bit Processor Functions
Data Sheet
In a special HDLC sub mode, the SCC provides transmission of PPP Data Link Layer
frames in either an asynchronous (start/stop), bit-synchronous or octet-synchronous
mode. An escape mechanism is implemented to allow control data such as XON/
XOFF to be transmitted transparently via the link, and to remove spurious control data
which may be injected into the link by intervening hardware and software.
Since all SCCs are contending for the internal busses, each SCC has an eight 32-bit
word deep FIFO in transmit and an seventeen 32-bit word deep FIFO in receive
direction for temporary storage of data packets transferred between the serial
communications interface and the central FIFOs of the DSCC4. These FIFOs allow
overlapping input/output operation (dual-port behavior).
In a special operating mode (clock mode 4, high speed mode) any of the four SCCs
can support high data rates: e.g. 45 Mbit/s for DS3 or 52 Mbit/s for OC1. The
aggregate bandwidth supported is 108 MBit/s per direction. This allows various
configurations, for example:
- 2 ports 52 MBit/s and 2 ports 2 MBit/s
- 2 ports 45 MBit/s and 2 ports 8 MBit/s
- 4 ports 26 MBit/s
– On chip clock generation or external clock source
– On chip DPLL for clock recovery
– Baud rate generator
– Programmable time-slot capability
– NRZ, NRZI, FM0/1 and Manchester data encoding
– Optional data flow control using modem lines (RTS, CTS, CD)
– Support of bus configuration by collision detection and resolution
– Full duplex data rates of up to 10 Mbit/s sync - 2 Mbit/s with DPLL, 2 Mbit/s async
– Full duplex data rate of up to 52 Mbit/s (HDLC address mode 0, PPP or extended
– HDLC/SDLC Mode
transparent mode) in clock mode 4 (external clock source and clock gating/
gapping).
- Automatic flag detection and transmission
- Shared opening and closing flag
- Generation of interframe-time fill ’1’ s or flags
- Detection of receive line status
- Zero bit insertion and deletion
- CRC generation and checking (CRC-CCITT or CRC-32)
Serial Communication Controller (SCC) Cores
129
PEB 20534
PEF 20534
2000-05-30