PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 414

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

13.6.1.2 PCI Write Transaction
The transaction starts when FRAME is activated (clock 2 in
transaction is similar to a read transaction except no turnaround cycle is required
following the address phase. In the example, the first and second data phases complete
with zero wait cycles. The third data phase has three wait cycles inserted by the target.
Both initiator and target insert a wait cycle on clock 5. In the case where the initiator
inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are
withdrawn. The last data phase is characterized by IRDY being asserted while the
FRAME signal is deasserted. This data phase is completed when TRDY goes active
(clock 8).
Figure 89
Data Sheet
CLK
FRAME
AD
C/BE
IRDY
TRDY
DEVSEL
1
PCI Write Transaction
Bus CMD
Address
Address
Phase
2
Data 1
BE’s-1
Phase
Data
3
Data 2
BE’s-2
Phase
Data
4
Bus Transaction
414
5
6
Phase
BE’s-3
Data
Electrical Characteristics
Data 3
7
Figure
8
PEB 20534
89). A write
PEF 20534
2000-05-30
ITD07576
9