PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 108

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Figure 29
Note: The DSCC4 will complete the currently running bus cycle before granting bus
Exiting the Hold State:
The external bus master returns the access rights to the DSCC4 EBC by driving the
LHOLD input high. After synchronizing this signal the EBC will drive the LHLDA output
high, actively drive the control signals and resume executing external bus cycles if
required.
Depending on the arbitration logic, the external bus can be returned to the EBC under
two circumstances:
• The external master does not require access to the shared resources and gives up its
• The DSCC4 EBC needs access to the shared resources and demands this by
Data Sheet
own access rights, or
activating its LBREQ output. The arbitration logic may then deactivate the other
master’s LHLDA and so free the external bus for the EBC, depending on the priority
of the different masters.
LHOLD
(input)
LHLDA
(output)
LBREQ
(output)
LCSO
(output)
LRD, LWR
(output signals)
access as indicated by the broken lines. This may delay hold acknowledge
compared to this figure.
The figure above shows the first possibility for LBREQ to become active.
External Bus Arbitration (Releasing the Bus)
108
Multi Function Port (MFP)
PEB 20534
PEF 20534
2000-05-30
ITD10615