PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 298

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
STOP
SLOAD
PAR(1..0)
PARE
Stop Bit number
This bit selects the number of stop bits per ASYNC character:
STOP=’0’
STOP=’1’
Enable SYNC Character Load
In BISYNC mode, SYNC characters might be filtered out or stored to the
SCC receive FIFO:
SLOAD=’0’
SLOAD=’1’
Parity Format
This bit field selects the parity generation/checking mode:
PAR = ’00’
PAR = ’01’
PAR = ’10’
PAR = ’11’
The received parity bit is stored in the SCC receive FIFO depending on
the selected character format:
• as leading bit immediately preceding the data bits if character length
• as LSB of the status byte belonging to the character if character length
A parity error is indicated in the MSB of the status byte belonging to each
character if enabled. In addition, a parity error interrupt can be
generated.
Parity Enable
PARE=’0’
PARE=’1’
is 5, 6 or 7 bits and bit ’DPS’ in register CCR2 is cleared (’0’).
is 8 bits and the corresponding receive FIFO data format is selected
(RFDF = ’1’).
1 stop bit per character.
2 stop bits per character.
SYNC characters are filtered out and not stored in the
receive FIFO.
All received characters including SYNC characters are
stored in the receive FIFO.
SPACE (’0’), a constant ’0’ is inserted as parity bit.
Odd parity.
Even parity.
MARK (’1’), a constant ’1’ is inserted as parity bit.
Parity generation/checking is disabled.
Parity generation/checking is enabled.
298
Detailed Register Description
(async/bisync modes)
(async/bisync modes)
(bisync mode)
(async mode)
PEB 20534
PEF 20534
2000-05-30