PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 258

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
RFTHRES
Mx
Receive FIFO Threshold
This bit field determins the central Receive FIFO Threshold in number of
DWORDs multiplied by its respective multiplier ’M2’ or ’M4’.
This threshold controls DMAC operation towards the Host memory.
A watermark is calculated by:
watermark = RFTHRES*Mx .
When more data than specified by this watermark are available in the
receive FIFO the DMA controller is requested to transfer the received
data to the channel specific data buffers in the host memory until the
central receive FIFO is empty. If no host memory buffer is available for
a channel, since the internal HOLD state is reached, i.e. ’HOLD’ bit has
been detected (GMODE.CMODE=’0’) or Last Descriptor Adress
matches the current descriptor address FRDA = LRDA
(GMODE.CMODE=’1’), no data can be transferred.
Note: The watermark has to be lower than the maximum central receive
Multiplier 2 or 4
These bits enable a multiplier 2 or 4 respectively for the ’RFTHRES’
value:
M2 = ’0’
M2 = ’1’
M4 = ’0’
M4 = ’1’
Note: It is recommended not to set both multiplier enable bits to ’1’.
FIFO size of 128 DWORDs.
The multiplier ’by 2’ is disabled
The ’RFTHRES’ bit field value is multiplied by 2.
The multiplier ’by 4’ is disabled
The ’RFTHRES’ bit field value is multiplied by 4.
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Detailed Register Description
PEB 20534
PEF 20534
2000-05-30
(-)
(-)