PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 222

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

10.2
According to the PCI Specification V2.1 the DSCC4 supports the register layout of the
predefined header region of the PCI Configuration Space.
Table 39
The predefined header region has a size of 64 bytes and consists of fields that uniquely
identify the device and allow the device to be controlled.
The DSCC4 supports the 64-byte header portion of the configuration space of PCI
Specification Rev 2.1 to identify the device upon initial installation and power-up. None
Data Sheet
Predefined header region of the PCI Configuration Space
31
Max_Lat (=0A
BAR1 (Base Address Register 1): base address of DSCC4 on-chip registers
BAR2 (Base Address Register 2): base address of Local Bus Interface
(=00
BIST
PCI Configuration Space - Detailed Register Description
Device ID (=2102
H
DSCC4: PCI Configuration Space Register Set
)
Status (=0280
H
)
Class Code (=028000
Min_Gnt (=03
Base Address Register 3 (not used)
Base Address Register 4 (not used)
Base Address Register 5 (not used)
Base Address Register 6 (not used)
Header Type
H
Expansion ROM Base Address
)
(=00
H
)
H
)
H
Reserved
Reserved
Reserved
Reserved
)
16 15
H
)
222
Interrupt Pin (=01
Latency Timer
(=00
Command (=0000
Vendor ID(=110A
H
)
Detailed Register Description
H
) Interrrupt Line (=00
Revision ID (=21
Cache Line Size
(=00
H
H
)
)
H
)
PEB 20534
PEF 20534
2000-05-30
H
)
H
0
)
0C
1C
2C
3C
00
04
08
10
14
18
20
24
28
30
34
38
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H