PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 285

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
SM(1..0)
VIS
PSD
Serial Port Mode
This bit field selects one of the three protocol engines.
Depending on the selected protocol engine the SCC related registers
change or special bit positions within the registers change their meaning.
SM = ’00’
SM = ’01’
SM = ’10’
SM = ’11’
Masked Interrupts Visible
VIS=’0’
VIS=’1’
Note: Masked interrupts will not generate an interrupt vector to the
DPLL Phase Shift Disable
This option is only applicable in the case of NRZ or NRZI line encoding
is selected.
PSD=’0’
PSD=’1’
interrupt controller.
HDLC/SDLC protocol engine
Reserved
(do not use)
BISYNC protocol engine
ASYNC protocol engine
Masked interrupt status bits are not visible on interrupt
status register (ISR) read accesses.
Masked interrupt status bits are visible and automatically
cleared after interrupt status register (ISR) read access.
Normal DPLL operation.
The phase shift function of the DPLL is disabled. The
windows for phase adjustment are extended.
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Detailed Register Description
PEB 20534
PEF 20534
(all modes)
(all modes)
(all modes)
2000-05-30