VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet - Page 67

• Manufacturer Part Number: VSC8641XKO
• Description: IC PHY 10/100/1000 100-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8641XKO

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Case: TQFP
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1031

Table 47.
4.3.14
Table 48.
Revision 4.3
August 2009
EPG Control Register 1, Address 29E (0x1D) (continued)
The following information applies to the EPG control number 1:
•
•
•
•
•
Ethernet Packet Generator Control 2
The register at address 30E consists of the second of bits that provide access to and
control over various aspects of the EPG testing feature. For information about the first
set of EPG control bits, see
available.
EPG Control Register 2, Address 30E (0x1E)
Note If any of bits 15:0 in this register are changed while the EPG is running (bit 14
of register 29E is set to 1), that bit (29E.14) must first be cleared and then set back to
1 for the change to take effect and to restart the EPG.
Bit
12:11
10
9:6
5:2
1
0
Bit
15:0
Do not run the EPG when the VSC8641 device is connected to a live network.
Bit 29E.13 (Continuous EPG mode control): When enabled, this mode causes the
device to send continuous packets. When disabled, the device continues to send
packets only until it reaches the next 10,000-packet increment mark. It then
ceases to send packets.
The six-byte destination address in bits 9:6 is assigned one of 16 addresses in the
range of 0xFF FF FF FF FF F0 through 0xFF FF FF FF FF FF.
The six-byte source address in bits 5:2 is assigned one of 16 addresses in the range
of 0xFF FF FF FF FF F0 through 0xFF FF FF FF FF FF.
If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14
must be cleared and then set back to 1 for the change to take effect and to restart
the EPG.
Name
EPG packet payload
Name
Packet length
Inter-packet gap
Destination address
Source address
Payload type
Bad frame check
sequence (FCS)
generation
Table 47,
Access
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
Description
Data pattern repeated in the payload of
packets generated by the EPG
page 66. The following table lists the settings
Description
00 = 125 bytes
01 = 64 bytes
10 = 1518 bytes
11 = 10,000 bytes (Jumbo packet)
1 = 8,192 ns
0 = 96 ns
Lowest nibble of the six-byte destination
address
Lowest nibble of the six-byte destination
address
1 = Randomly generated payload pattern
0 = Fixed based on payload pattern
1 = Generate packets with bad FCS
0 = Generate packets with good FCS
VSC8641 Datasheet
Configuration
Default
Default
0x00
Page 67
0001
0000
0
0
0
0