VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet - Page 30

• Manufacturer Part Number: VSC8641XKO
• Description: IC PHY 10/100/1000 100-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8641XKO

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Case: TQFP
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1031

Figure 10.
3.11.2
Revision 4.3
August 2009
MDIO
MDC
Idle
Z
Z
Preamble
(optional)
1
0
SFD
SMI Write Frame
The following provides additional information about the terms used in the illustrations.
Idle During idle, the MDIO node goes to a high-impedance state. This allows an
external pull-up resistor to pull the MDIO node up to a logical 1 state. Because the idle
mode should not contain any transitions on MDIO, the number of bits is undefined
during idle.
Preamble
string of ones. If it exists, the preamble must be at least one bit; otherwise, it may be
of an arbitrary length.
Start of Frame (SFD)
not 01, all following bits are ignored until the next preamble pattern is detected.
Read or Write Opcode
write. If these bits are not either 01 or 10, all following bits are ignored until the next
preamble pattern is detected.
PHY Address
PHY address matches its physical address. The physical address is five bits long (4:0).
The bits are set by the CMODE pins.
Register Address The next five bits are the register address.
Turn-around The two bits used to avoid signal contention when a read operation is
performed on the MDIO are called the turn-around (TA) bits. During read operations,
the VSC8641 device drives the second TA bit, which is a logical 0.
Data
stream. When data is read from a PHY, it is valid at the output from one rising edge of
MDC to the next rising edge of MDC. When data is being written to the PHY, it must be
valid around the rising edge of MDC.
Idle The sequence is repeated.
SMI Interrupts
The SMI also includes an output interrupt signal, MDINT, for signaling the station
manager when certain events occur in the PHY.
The MDINT pin can be configured for open-drain (active-low) by tying the pin to a pull-
up resistor and to VDDIO. The following illustration shows this configuration.
1
0
Write
1
The 16-bits read from or written to the device are considered the data or data
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHY Address
By default, preambles are not expected nor required. The preamble is a
The VSC8641 responds to a message frame only when the received
Station Manager Drives MDIO (PHY tristates MDIO during entire sequence)
Register Address
A pattern of 01 indicates the start of frame. If the pattern is
to PHY
A pattern of 10 indicates a read. A pattern of 01 indicates a
1
TA
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register Data from PHY
Functional Descriptions
VSC8641 Datasheet
Page 30
Z
Idle
Z