VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet - Page 53

no-image

VSC8641XKO

Manufacturer Part Number
VSC8641XKO
Description
IC PHY 10/100/1000 100-LQFP
Manufacturer
Vitesse Semiconductor Corp
Type
PHY Transceiverr
Datasheets

Specifications of VSC8641XKO

Number Of Drivers/receivers
1/1
Protocol
Gigabit Ethernet
Voltage - Supply
2.5V, 3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Case
TQFP
Dc
07+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
907-1031

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
VSC8641XKO
Manufacturer:
MICRON
Quantity:
120
Part Number:
VSC8641XKO
Manufacturer:
VITESSE45
Quantity:
1 390
Part Number:
VSC8641XKO
Manufacturer:
Vitesse Semiconductor Corporation
Quantity:
10 000
Part Number:
VSC8641XKO
Manufacturer:
VITESSE
Quantity:
20 000
Part Number:
VSC8641XKO-03
Manufacturer:
VITESSE
Quantity:
5 144
Part Number:
VSC8641XKO-03
Manufacturer:
VITESSE23
Quantity:
4 024
Company:
Part Number:
VSC8641XKO-03
Quantity:
30
4.2.20
Table 27.
Revision 4.3
August 2009
Extended PHY Control Set 1
The bits in the extended control set control the MAC auto-negotiation functioning,
SGMII alignment errors, and EEPROM status. The following table lists the settings
available.
Extended PHY Control 1, Address 23 (0x17)
Note After configuring bit 12 of the extended PHY control register set 1, a software
reset (register 0, bit 15) must be written to change the device operating mode. Bit 1
allows for flexibility in printed circuit board layouts because it can reorder the TXD pins.
Bit
15:13
12
11:9
8
7:6
5
4:2
1
0
When bits 11:0 are set to 00, the squelch threshold levels are based on the IEEE
standard for 10BASE-T. When set to 01, the squelch level is decreased, which may
improve the bit error rate performance on long loops. When set to 10, the squelch
level is increased and may improve the bit error rate in high-noise environments.
Name
Reserved
MAC interface mode
select
Reserved
RGMII skew timing
compensation
enable
Reserved
ActiPHY mode
enable
Reserved
GMII transmit pin
reversal
Reserved
Access
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
Description
This is a super-sticky bit.
0 = GMII MAC interface mode.
1 = RGMII MAC interface mode.
This is a sticky bit.
0 = Disabled.
1 = Adds 1.7 ns delay to the RX_CLK and
TX_CLK pins.
Note There is a design consideration
associated with this register. For more
information, see
RGMII Timing Compensation Value,”
page 121.
This is a sticky bit.
1 = Enabled.
This is a sticky bit.
0 = GMII transmit pin order default.
1 = GMII transmit pin order reversed.
“Setting the Internal
VSC8641 Datasheet
Configuration
Default
Page 53
CMODE
CMODE
CMODE
0

Related parts for VSC8641XKO