VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet - Page 12

• Manufacturer Part Number: VSC8641XKO
• Description: IC PHY 10/100/1000 100-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8641XKO

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Case: TQFP
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1031

Revision 2.3
Revision 4.3
August 2009
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Revision 2.3 of this datasheet was published in July 2006. The following is a summary
of the changes implemented in the datasheet:
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In the AC characteristics for the CLKOUT pin, the duty cycle (%
from 40% minimum to 44% minimum and from 60% maximum to 56% maximum.
Also, the total jitter (J
with the qualifier “time interval error” added to the condition.
In the SMI specifications, the MDC rise and fall times were corrected from minimum
values to maximum values.
For the device reset rise time specification, a condition was added that it is
measured from a 10% level to a 90% level.
In the AC characteristics for RGMII uncompensated, the 1000BASE-T duty cycle
(t
the same, but the added condition is: at room temperature and nominal supply and
register 28E.13:12 set to 10 or 11. In the second set, the minimum is 40% and the
maximum is 60% and the condition is: register 28E.13:12 set to 00 or 01.
In the AC characteristics for RGMII compensated, all of the setup and hold times
were modified from 0 ns to 3 ns.
The electrostatic discharge voltage values were added. For charged device model, it
is ±500 V. For human body model, it is ±1750 V.
In the description of pin MDIO, the type was corrected from open drain (OD) to
input and output (I/O).
The PLLMODE pin description was updated with additional clocking information. If a
crystal or an external 25 MHz clock is used, PLLMODE must be pulled low. If an
external 125 MHz clock is used, PLLMODE must be pulled high.
The moisture sensitivity is now specified as level 3.
A design guideline was added regarding writes from the serial management
interface (SMI) after a software reset.
In the inline powered Ethernet switch diagram, a reference to “SGMII interface”
was corrected to “RGMII interface.”
In the description of CRC counters, the CRC good counter’s highest value was
corrected from 10,000 to 9,999 packets, after which the counter clears.
The device revision number definition was updated from 0000 to 0001 in the
identifier 2 register (address 3) and the JTAG device identification.
In the DC Characteristics for V
leakage (I
(I
were changed from –10 µA minimum and 10 µA maximum to –36 µA minimum and
36 µA maximum.
DUTY1000
ILEAK
) with the same condition (internal resistor included). Specifically, the values
) was separated into two sets of values. In the first set, the values remain
OLEAK
) was changed to match the same values as the input leakage
CLK
) was raised from 491 ps maximum to 600 ps maximum,
DD33
, V
DDIOMAC
, or V
DDIOMICRO
at 3.3 V, the output
VSC8641 Datasheet
DUTY
Revision History
) was modified
Page 12