VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet
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VSC8641 10/100/1000BASE-T PHY with RGMII and GMII MAC Interface Datasheet VMDS-10211 Revision 4.3 August 2009 ...
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... United States www.vitesse.com Copyright© 2005–2009 by Vitesse Semiconductor Corporation Vitesse Semiconductor Corporation (“Vitesse”) retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time ...
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Contents Revision History ........................................................................................10 1 Introduction.....................................................................................16 2 Product Overview.............................................................................17 2.1 Features ........................................................................................................... 17 2.2 Applications....................................................................................................... 18 2.3 Block Diagram ................................................................................................... 19 3 Functional Descriptions....................................................................20 3.1 Operating Modes ................................................................................................ 20 3.2 MAC Interface.................................................................................................... 20 3.2.1 MAC Resistor Calibration .......................................................................... 20 3.2.2 ...
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Mode Status........................................................................................... 43 4.2.3 Device Identification ............................................................................... 44 4.2.4 Auto-Negotiation Advertisement ............................................................... 44 4.2.5 Link Partner Auto-Negotiation Capability .................................................... 45 4.2.6 Auto-Negotiation Expansion ..................................................................... 46 4.2.7 Transmit Auto-Negotiation Next Page......................................................... 46 4.2.8 Auto-Negotiation Link Partner Next Page Receive ........................................ ...
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... Miscellaneous....................................................................................... 109 6.6.6 Power Supply ....................................................................................... 110 6.6.7 Power Supply and Associated Function..................................................... 111 6.7 Pins by Number (VSC8641XKO, VSC8641XKO-03) ................................................ 112 6.8 Pins by Name (VSC8641XKO, VSC8641XKO-03) ................................................... 113 7 Package Information......................................................................114 7.1 Package Drawings ............................................................................................ 114 7.2 Thermal Specifications ...................................................................................... 117 7.3 Moisture Sensitivity .......................................................................................... 117 8 Design Considerations ...
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Default 10Base-T Settings Are Marginal and Cause MAU Test Failure........................ 119 8.5 On-Chip Pull-up Resistor Violation....................................................................... 121 8.6 Setting the Internal RGMII Timing Compensation Value ......................................... 121 8.7 10BASE-T Harmonics at 30 MHz and 50 MHz Marginally Violate Specification ...
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... Figure 25. MII Receive Timing..................................................................................... 88 Figure 26. RGMII Uncompensated Timing ..................................................................... 89 Figure 27. RGMII Compensated Timing ........................................................................ 91 Figure 28. Pin Diagram for VSC8641XJF ....................................................................... 94 Figure 29. Pin Diagram for VSC8641XKO and VSC8641XKO-03 ..................................... 104 Figure 30. Package Drawing for VSC8641XJF .............................................................. 115 Figure 31. Package Drawing for VSC8641XKO and VSC8641XKO-03............................... 116 Revision 4.3 ...
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Tables Table 1. Operating Modes........................................................................................ 20 Table 2. Supported MDI Pair Combinations ................................................................ 25 Table 3. LED Mode and Function Summary ................................................................ 32 Table 4. JTAG Device Identification Register Description .............................................. 39 Table 5. JTAG Interface Instruction Codes ................................................................. 39 ...
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Table 54. DC Characteristics for VDDIOMAC or VDDIOMICRO at 2.5 V............................. 74 Table 55. Current Consumption: 1000BASE-T, Regulator Enabled ................................... 74 Table 56. Current Consumption: 1000BASE-T, Regulator Disabled................................... 75 Table 57. Current Consumption: 100BASE-TX, Regulator Enabled ................................... 76 Table 58. ...
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Revision History This section describes the changes that were implemented in this document. The changes are listed by revision, starting with the most current publication. Revision 4.3 Revision 4.3 of this datasheet was published in August 2009. The following is ...
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... Revision 4.0 Revision 4.0 of this datasheet was published in December 2006. The following is a summary of the changes implemented in the datasheet: • The VSC8641KO package was removed from the datasheet. VSC8641XKO remains available. • In the jumbo packet register settings (28E.11:10), the packet lengths were updated. • ...
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In the AC characteristics for the CLKOUT pin, the duty cycle (% from 40% minimum to 44% minimum and from 60% maximum to 56% maximum. Also, the total jitter (J with the qualifier “time interval error” added to the ...
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In the DC Characteristics for was changed to match the same values as the input leakage (I OLEAK the same condition (internal resistor included). Specifically, the values were changed from –10 µA minimum and 10 µA ...
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The VSC8641 device switches between the low-power state and LP wake-up state every two seconds; the rate is not programmable, as was originally stated. • In the link partner wake-up state, the device sends FLP bursts for two seconds; ...
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In the stress ratings, a new rating was added for the VDDREG parameter. • In the section describing the device pins associated with the GMII/RGMII MAC interface, the term “GMII” was missing now included in the heading ...
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Introduction This document consists of descriptions and specifications for both functional and physical aspects of the VSC8641 device. In addition to the datasheet, Vitesse maintains an extensive device-specific library of support and collateral materials that you may find useful ...
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Product Overview The VSC8641 device is a low-power Gigabit Ethernet (GbE) transceiver ideal for Gigabit LAN-on-Motherboard applications. The device’s compact, plastic low-profile quad flat package (LQFP) or quad flat no-lead (QFN) package with an exposed pad is optimal for ...
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Legacy Power-over-Ethernet (POE) support. • Powered by a single 3.3 V supply by using the optional on-chip switching regulator. • IEEE 1149.1 JTAG boundary-scan support. • × 10 mm, 88-pin, plastic QFN package with an exposed pad. ...
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Block Diagram The following illustration shows the primary functional blocks of the VSC8641 device. Figure 2. High-level Block Diagram GTX_CLK TX_CLK TXD[7:0] TX_EN R/GMII TX_ER Jumbo Packet MAC CRS FIFO COL Interface RX_CLK RXD[7:0] RX_DV RX_ER CMODE[4:0] NRESET NSRESET ...
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Functional Descriptions This section provides detailed information about how the VSC8641 device works, what configurations and operational features are available, and how to test its functions. It includes descriptions of the various device interfaces and how to set them ...
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Figure 4. RGMII MAC Interface RGMII MAC TD[3] TD[2] TD[1] TD[0] TXC TX_CTL RD[3] RD[2] RD[1] RD[0] RXC RX_CTL 3.2.3 GMII/MII MAC Interface Mode The GMII/MII interface can support all three speeds (10 Mbps, 100 Mbps, and 1000 Mbps) and ...
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Figure 5. GMII/MII MAC Interface GMII/MII MAC TXD[ 7] TXD[ 6] TXD[ 5] TXD[ 4] TXD[ 3] TXD[ 2] TXD[ 1] TXD[ 0] TX_CLK GTX_CLK TX_ER TX_EN COL CRS RXD[ 7] RXD[ 6] RXD[ 5] RXD[ 4] RXD[ 3] RXD[ ...
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Figure 6. Cat5 Media Interface SimpliPHY TXVP_A_n TXVN_A_n TXVP_B_n TXVN_B_n TXVP_C_n TXVN_C_n TXVP_D_n TXVN_D_n 3.4 Cat5 Auto-Negotiation The VSC8641 device supports twisted pair auto-negotiation as defined by clause 28 of the IEEE standard 802.3-2000. The auto-negotiation process consists of the ...
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Manual MDI/MDI-X Setting As an alternative to automatic MDI/MDI-X detection (using HP Auto-MDIX technology), you can force the PHY to select MDI or MDI-X using the following scripts. Format: Phywrite ( register(dec), data(hex) ) Phywritemask ( register(dec), data(hex), mask(hex) ...
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The VSC8641 device’s algorithm for HP Auto-MDIX successfully detects, corrects, and operates with any of the MDI wiring pair combinations listed in the following table. Table 2. Supported MDI Pair Combinations RJ-45 Pin Pairings ...
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The VSC8641 device is compatible with switch designs that are intended for use in systems that supply power to Data Terminal Equipment (DTE) using the MDI or twisted pair cable, as described in clause 33 of the IEEE standard 802.3af. ...
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device does not loop back the FLP after a specific time, VSC8641 device register bit 23E.9:8 automatically resets to 10 the VSC8641 PHY reports that the LP ...
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Figure 8. ActiPHY State FLP Burst Signal Sent LP Wake-up State 3.10.1 Low-Power State In the low-power state, all major digital blocks are powered down. However, the following functionality is provided: • SMI interface (MDC, MDIO, MDINT) • CLKOUT In ...
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In this state, the following functionality is provided: • SMI interface (MDC, MDIO, MDINT) • CLKOUT After sending signal energy on the relevant media, the PHY returns to the low-power state. 3.10.3 Normal Operating State In this state, the PHY ...
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Figure 10. SMI Write Frame MDC MDIO Idle Preamble SFD Write PHY Address (optional) The following provides additional information about the terms used ...
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Figure 11. MDINT Configured as an Open-Drain (Active-Low) Pin Interrupt Pin Enable (MII Register 25.15) Interrupt Pin Status (MII Register 26.15) Alternatively, each MDINT pin can be configured for open-source (active-high) by tying the pin to a pull-down resistor and ...
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For added flexibility, the VSC8641 LED can be controlled using the enhanced LED method. The enhanced LED method is enabled by setting MII Register 17E When enabled, then the LEDs are controlled by MII Registers 16E and 17E. ...
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Table 3. LED Mode and Function Summary (continued) Mode Function Name 6 Link10/100/activity 7 Reserved 8 Duplex/collision 9 Collision 10 Activity 11 Reserved 12 Auto-negotiation fault 13 Reserved 14 Force LED off 15 Force LED on 3.12.3 LED Behavior Several ...
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LED Pulsing Enable To provide additional power savings, the LEDs (when asserted) can be pulsed at 5 kHz, 20% duty cycle. 3.13 Testing Features The VSC8641 device includes several testing features designed to make it easier to perform system-level debugging ...
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After receiving a packet on the media interface, register bit 18E.15 is set and cleared after being read. The packet then is counted by either the CRC good counter or the CRC error counter. Both CRC counters are also ...
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Connector Loopback The connector loopback testing feature allows for the twisted pair interface to be looped back externally. When using this feature, the PHY must be connected to a loopback connector or a loopback cable. Pair A should be ...
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These conditions can all prevent the device from establishing a link at any speed. Cable Pair Termination impedance between the positive and negative cable terminals. The IEEE standard 802.3 allows for a termination of as ...
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Figure 16. Test Access Port and Boundary-Scan Architecture TDI TMS Test Access Port NTRST TCK After a TAP reset, the Device Identification register is serially connected between TDI and TDO by default. The TAP Instruction register is loaded either from ...
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IDCODE Provides the version number (bits 31:28), part number (bits 27:12), and the manufacturer identity (bits 11: serially read from the device. The following table provides information about the meaning of IDCODE binary values stored in the device ...
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Configuration The VSC8641 device can be configured using three different methods: • Setting internal memory registers using the management interface. • Setting a combination of CMODE pins and registers. • Loading a configuration into an external EEPROM and connecting ...
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Reserved Registers For main registers 16 through 31 and extended page registers 16E through 30E, any bits marked as “Reserved” should be processed as read only and their states as undefined. 4.1.2 Reserved Bits In writing to registers with ...
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Table 7. Main Registers (continued) Register Address 4.2.1 Mode Control The device register at memory address 0.00.15:0 controls several aspects of VSC8641 functionality. The following table ...
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Table 8. Mode Control, Address 0 (0x00) (continued) Bit Name 11 Power-down 10 Isolate 9 Restart auto- negotiation 8 Duplex 7 Collision test enable 6 MSB for speed selection 5:0 Reserved 4.2.2 Mode Status The register at 1.01.15:0 in the ...
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Table 9. Mode Status, Address 1 (0x01) (continued) Bit Name 4 Remote fault 3 Auto-negotiation capability 2 Link status 1 Jabber detect 0 Extended capability 4.2.3 Device Identification All 16 bits in both register 2 and register 3 in the ...
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Table 12. Device Auto-Negotiation Advertisement, Address 4 (0x04) Bit Name 12 Reserved technologies 11 Advertise asymmetric pause 10 Advertise symmetric pause 9 Advertise 100BASE-T4 8 Advertise 100BASE-TX FDX 7 Advertise 100BASE-TX HDX 6 Advertise 10BASE-T FDX 5 Advertise 10BASE-T HDX ...
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Auto-Negotiation Expansion The bits in main register 6 work together with those in register 5 to indicate the status of the LP auto-negotiation. The following table lists the available settings and readouts. Table 14. Auto-Negotiation Expansion, Address 6 (0x06) ...
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Table 16. Auto-Negotiation LP Next Page Receive, Address 8 (0x08) (continued) Bit Name 14 Acknowledge 13 LP message page 12 LP Acknowledge toggle 10:0 LP message / unformatted code 4.2.9 1000BASE-T Control The VSC8641 device’s 1000BASE-T functionality ...
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Status The bits in register 10 of the main register space allow you to read the status of the 1000BASE-T communications enabled in the device. The following table lists these readouts. Table 18. 1000BASE-T Status, Address 10 (0x0A) ...
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Status Extension Register 16 in the main registers page space of the VSC8641 device provides additional information about the status of the device’s 100BASE-TX operation. Table 20. 100BASE-TX Status Extension, Address 16 (0x10) Bit Name 15 100BASE-TX descrambler ...
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Table 21. 1000BASE-T Status Extension 2, Address 17 (0x11) (continued) Bit Name 9 1000BASE-T SSD error 8 1000BASE-T ESD error 7 1000BASE-T carrier extension error 6 Non-compliant BCM5400 detected 5 MDI crossover error 4:0 Reserved 4.2.15 Bypass Control The bits ...
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Note If bit 1 is set this register, automatic exchange of next pages is disabled, and control is returned to the user through the SMI after the base page is exchanged. The user then must send the ...
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Disconnect Counter The following table lists the readouts you can expect. Table 25. Disconnect Counter, Address 21 (0x15) Bit Name 15:8 Reserved 7:0 Disconnect counter 4.2.19 Extended Control and Status The bits in register 22 provide additional device control ...
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When bits 11:0 are set to 00, the squelch threshold levels are based on the IEEE standard for 10BASE-T. When set to 01, the squelch level is decreased, which may improve the bit error rate performance on long loops. ...
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Extended PHY Control Set 2 The second set of extended controls is located in register 24 in the main register space for the device. The following table lists the settings and readouts available. Table 28. Extended PHY Control 2, ...
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Table 29. Interrupt Mask, Address 25 (0x19) (continued) Bit Name 2 Link speed downshift detect mask 1 Master/Slave resolution error mask 0 Reserved Note When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this ...
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LED Control If you are using the simple LED method of control, you can control the LEDs using the following settings. If you are using the enhanced LED method, there are different register settings you can use. For information ...
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Auxiliary Control and Status The following table lists the settings available. Table 32. Auxiliary Control and Status, Address 28 (0x1C) Bit Name 15 Auto-negotiation complete 14 Auto-negotiation disabled 13 MDI/MDI-X crossover indication 12 CD pair swap 11 A polarity ...
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Table 33. Delay Skew Status, Address = 29 (0x1D) (continued) Bit Name 10:8 Pair B delay skew 7 Reserved 6:4 Pair C delay skew 3 Reserved 2:0 Pair D delay skew 4.2.27 Reserved Address Space The bits in register 30 ...
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Table 34. Extended Registers Page Space (continued) Register Address 28E 29E 30E 4.3.1 Extended Page Access The register at address 31 controls the access to the extended page registers for the VSC8641 device. The following table lists the settings available. ...
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Table 37. Available LED Mode Settings (continued) Mode Bit Setting 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 Reserved 12 1100 13 Reserved 14 1110 15 1111 4.3.3 Enhanced LED Behavior ...
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Table 38. Enhanced LED Behavior, Address 17E (0x11) (continued) Bit Name 4 LED mode 3 LED3 combine feature disable 2 LED2 combine feature disable 1 LED1 combine feature disable 0 LED0 combine feature disable Note Bit 4 must be set ...
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MAC Resistor Calibration Control The following table lists the settings available. Table 40. MAC Resistor Calibration Control, Address 19E (0x13) Bit Name 15:14 MAC resistor calibration control setting 13:0 Reserved 4.3.6 Extended PHY Control 3 Register 20E controls the ...
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Table 41. Extended PHY Control 3, Address 20E (0x14) (continued) Bit Name 1 Link speed auto-downshift status 0 Reserved 4.3.7 EEPROM Interface Status and Control Register 21E is used to affect control over device function when you have incorporated a ...
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Extended PHY Control 4 The register at address 23E consists of the fourth set bits that control various aspects of inline powering and the CRC error counter in the VSC8641 device. Table 44. Extended PHY Control 4, Address 23E ...
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Table 45. Extended PHY Control 5, Address 27E (0x1B) (continued) Bit Name 13:12 CRS behavior control 11 EEPROM present 10 Far End loopback mode 9 PICMG 2.16 reduced power mode 8:6 100BASE-TX transmitter amplitude control 5:3 1000BASE-T transmitter amplitude control ...
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RGMII Skew Control The following table lists the settings available. Table 46. RGMII Skew Control, Address 28E (0x1C) Bit Name 15:14 RGMII TX skew compensation enable 13:12 RGMII RX skew compensation enable 11:10 Jumbo packet mode 9 10BASE-T no ...
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Table 47. EPG Control Register 1, Address 29E (0x1D) (continued) Bit Name 12:11 Packet length 10 Inter-packet gap 9:6 Destination address 5:2 Source address 1 Payload type 0 Bad frame check sequence (FCS) generation The following information applies to the ...
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... CMODE pins to control the device function. There are five configuration mode (CMODE) pins on the VSC8641 device. For more information about the physical location of the CMODE pins, see (VSC8641XKO, VSC8641XKO-03),” bit, which means there are 20 possible settings for the device. 4.4.1 ...
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Table 50. Device Functions and Associated CMODE Pins (continued) CMODE Function Pin Advertise 0 asymmetric pause Advertise 0 symmetric pause CLKOUT enable 0 ActiPHY 2 LED combine/ 4 separate MAC resistor 3 1 and 0 calibration setting LED3 control 4 ...
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Table 51. CMODE Resistor Values and Resultant Bit Settings (continued) With CMODE Pin Tied To VDD33 VDD33 VDD33 VDD33 Using resistors with the CMODE pins can be optional in designs that access the device’s MDC/MDIO pins. In designs that do ...
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Data is read from the EEPROM sequentially until all SMI write commands are completed. Table 52. EEPROM Configuration Contents 10-bit Address K+1 X X+1 X+2 X+3 X+4 X+5 X+6 X+7 X+(M–2) X+(M–1) X+M ...
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Figure 18. EEPROM Read and Write Register Flow Write EEPROM Data 21E. 21E.10:0 = Write Address 21E. 22E.7:0 = Data to Write To read a value from a specific address of the EEPROM: 1. Read the ...
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Electrical Specifications This section provides the DC characteristics, AC characteristics, recommended operating conditions, and stress ratings for the VSC8641 device. It includes information on the various timing functions of the device. 5.1 DC Characteristics In addition to any parameter-specific ...
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VDDIO at 2 addition to any parameter-specific conditions, the specifications listed in the following table may be considered valid only when all of these apply: • 2.5 V DDIO • 3.3 V DD33 ...
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Table 55. Current Consumption: 1000BASE-T, Regulator Enabled (continued) Parameter Current with V DDIOMAC Current with V DDIOMAC Current with V DDIOMICRO Current with V DDIOMICRO Total power at 3.3 V Total power at 2.5 V The following table shows the ...
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Consumption with 100BASE-TX Link The following table shows the current consumption values with a 100BASE-TX link and the on-chip switching regulator enabled. Table 57. Current Consumption: 100BASE-TX, Regulator Enabled Parameter Current with V DD33 Current with V DDREG Current ...
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Consumption with 10BASE-T Link The following table shows the current consumption values with a 10BASE-T link and the on-chip switching regulator enabled. Table 59. Current Consumption: 10BASE-T, Regulator Enabled Parameter Current with V DD33 Current with V DDREG Current ...
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Consumption with No Link and ActiPHY Enabled The following table shows the current consumption values with no link, ActiPHY enabled, and the on-chip switching regulator enabled. Table 61. Current Consumption: No Link, ActiPHY Enabled, Regulator Enabled Parameter Current with ...
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Consumption with No Link and ActiPHY Disabled The following table shows the current consumption values with no link, ActiPHY disabled, and the on-chip switching regulator enabled. Table 63. Current Consumption: No Link, ActiPHY Disabled, Regulator Enabled Parameter Current with ...
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Consumption in Power-Down Mode The following table shows the current consumption values in power-down mode (register address 0. with the regulator enabled. Table 65. Current Consumption: Power-Down, Regulator Enabled Parameter Current with V DD33 Current with V ...
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Table 67. Current Consumption: Reset State (continued) Parameter Current with V DDIOMAC Current with V DDIOMICRO Current with V DDIOMICRO Total power at 3.3 V 5.3 AC Characteristics The AC specifications are grouped according to specific device pins and associated ...
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Table 70. AC Characteristics for the CLKOUT Pin (continued) Parameter CLKOUT cycle time Frequency stability Duty cycle Clock rise and fall times (20% to 80%) Total jitter 5.3.3 JTAG Interface The following table lists the characteristics for the JTAG testing ...
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Figure 19. JTAG Interface Timing TCK TDI TMS TDO 5.3.4 SMI Interface Use the information in the following table when incorporating the VSC8641 device SMI interface into your own design. For information about the SMI interface timing, see Figure 20, ...
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Figure 20. SMI Interface Timing MDC MDIO (write) MDIO (read) 5.3.5 Device Reset The following specifications apply to the device reset functionality. For information about the reset timing, see Table 73. AC Characteristics for Device Reset Parameter Symbol NRESET assertion ...
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Figure 21. Reset Timing t VDDSTABLE VDD33 REFCLK NRESET NSRESET Soft Reset Undefined State (MII Register 0.15) MDC MDIO Note The NRESET and NSRESET are mutually exclusive. 5.3.6 GMII Transmit The following table lists the characteristics when using the device ...
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Figure 22. GMII Transmit Timing GTX_CLK t HIGH TXD[7:0] TX_EN TX_ER 5.3.7 GMII Receive The following table lists the characteristics when using the device in GMII receive mode. For information about the GMII receive timing, see Table 75. AC Characteristics ...
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Figure 23. GMII Receive Timing RX_CLK t HIGH RXD[7:0] RX_DV RX_ER 5.3.8 MII Transmit The following table lists the characteristics when using the device in MII transmit mode. For information about the MII transmit timing, see Table 76. AC Characteristics ...
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MII Receive The following table lists the characteristics when using the device in MII receive mode. For information about the MII receive timing, see Table 77. AC Characteristics for MII Receive Parameter Setup to RX_CLK rising Hold from RX_CLK ...
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Table 78. AC Characteristics for RGMII Uncompensated (continued) Parameter TX_CLK switching threshold TX_CLK rise and fall times Figure 26. RGMII Uncompensated Timing TX_CLK (at Transmitter) TXD[3:0] TX_CTL TX_CLK (at Receiver) RX_CLK (at Transmitter) RXD[3:0] RX_CTL RX_CLK (at Receiver) Revision 4.3 ...
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RGMII Compensated The following table lists the characteristics when using the device in RGMII compensated mode. For information about the RGMII compensated timing, see Figure 27, page 91. Table 79. AC Characteristics for RGMII Compensated Parameter Data to clock ...
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Figure 27. RGMII Compensated Timing Delay = 2.0 ns TX_CLK (at Transmitter) TXD[3:0] TX_CTL TX_CLK (at Receiver) Delay = 2.0 ns RX_CLK (at Transmitter) RXD[3:0] RX_CTL RX_CLK (at Receiver) 5.4 Operating Conditions The following table lists the recommended operating conditions ...
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Table 80. Recommended Operating Conditions (continued) Parameter Power supply voltage for V VSC8641 operating temperature VSC8641-03 operating (1) temperature 1. Lower limit of specification is ambient temperature, and upper limit is case temperature. 5.5 Stress Ratings This section contains the ...
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... Pin Descriptions The VSC8641 device is available in two package types. VSC8641XJF is an 88-pin package. VSC8641XKO and VSC8641XKO-03 are 100-pin packages. This section contains the pin descriptions. The pin information is also provided as attached Microsoft Excel files. This allows you to copy the information electronically. In Adobe Reader, double-click the attachment icon ...
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Pin Diagram (VSC8641XJF) The following illustration shows the pin diagram for the VSC8641XJF device. Note The exposed pad is internally connected to ground and should be connected to VSS on the board as well. Figure 28. Pin Diagram for ...
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Pins By Function (VSC8641XJF) This section contains the functional pin descriptions for the VSC8641XJF device. 6.2.1 Twisted Pair Interface The following table lists the device pins associated with the device two-wire, twisted pair interface. Table 83. Twisted Pair Interface ...
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Table 84. GMII/RGMII MAC Interface Pins (continued) Pin Name 22 RX_ER 21 RX_DV 36 TXD7 37 TXD6 38 TXD5 39 TXD4 40 TXD3 41 TXD2 42 TXD1 43 TXD0 34 TX_CLK 35 GTX_CLK Revision 4.3 August 2009 Type Description O ...
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Table 84. GMII/RGMII MAC Interface Pins (continued) Pin Name 44 TX_ER 47 TX_EN 17 CRS 18 COL 45 NSRESET Revision 4.3 August 2009 Type Description I GMII Mode: (TX_ER) PD Transmit error. This input is sampled by the PHY on ...
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Table 84. GMII/RGMII MAC Interface Pins (continued) Pin Name 59 OSCEN/CLKOUT 6.2.3 Serial Management Interface (SMI) The following table lists the device pins associated with the device serial management interface (SMI). Note that the pins in this table except NRESET ...
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Table 85. SMI Pins (continued) Pin Name 11 EECLK 9 NRESET 6.2.4 JTAG The following table lists the device pins associated with the device JTAG testing facility. Table 86. JTAG Pins Pin Name 4 TDI 3 TDO 6 TMS 7 ...
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Table 87. Miscellaneous Pins (continued) Pin Name 64 PLLMODE 55 LED3 56 LED2 57 LED1 58 LED0 70 REF_REXT 69 REF_FILT 60 REG_EN 62, 63 REG_OUT 65 NC 6.2.6 Power Supply The following table lists the device power supply pins. ...
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Power Supply and Associated Function Although certain function pins may not be used for a specific application, all power supply pins must be connected to their respective voltage input. Table 89. Power Supply Pins and Associated Function Pins Pins ...
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Pins by Number (VSC8641XJF) This section provides a numeric list of the VSC8641XJF pins. 1 VDD33 2 VDD33 3 TDO 4 TDI 5 VDD12 6 TMS 7 TCK 8 NTRST 9 NRESET 10 EEDAT 11 EECLK 12 VDDIOMICRO 13 ...
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Pins by Name (VSC8641XJF) This section provides an alphabetical list of the VSC8641XJF pins. CMODE0 CMODE1 CMODE2 CMODE3 CMODE4 COL CRS EECLK EEDAT GTX_CLK LED0 LED1 LED2 LED3 MDC MDINT MDIO NC NRESET NSRESET NTRST OSCEN /CLKOUT PLLMODE REF_FILT ...
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... Pin Diagram (VSC8641XKO, VSC8641XKO-03) The following illustration shows the pin diagram for the VSC8641XKO and VSC8641XKO-03 devices. Note The exposed pad is internally connected to ground and should be connected to VSS on the board as well. Figure 29. Pin Diagram for VSC8641XKO and VSC8641XKO- VDD33 3 VDD33 ...
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... Pins by Function (VSC8641XKO, VSC8641XKO-03) This section contains the functional pin descriptions for the VSC8641XKO and VSC8641XKO-03 devices. 6.6.1 Twisted Pair Interface The following table lists the device pins associated with the device two-wire, twisted pair interface. Table 90. Twisted Pair Interface Pins ...
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Table 91. GMII/RGMII MAC Interface Pins (continued) Pin Name 27 RX_ER 26 RX_DV 41 TXD7 42 TXD6 43 TXD5 44 TXD4 45 TXD3 46 TXD2 47 TXD1 48 TXD0 39 TX_CLK 40 GTX_CLK Revision 4.3 August 2009 Type Description O ...
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Table 91. GMII/RGMII MAC Interface Pins (continued) Pin Name 49 TX_ER 54 TX_EN 21 CRS 22 COL 50 NSRESET Revision 4.3 August 2009 Type Description I GMII Mode: (TX_ER) PD Transmit error. This input is sampled by the PHY on ...
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Table 91. GMII/RGMII MAC Interface Pins (continued) Pin Name 66 OSCEN/CLKOUT 6.6.3 Serial Management Interface (SMI) The following table lists the device pins associated with the device serial management interface (SMI). Note that the pins in this table except NRESET ...
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JTAG The following table lists the device pins associated with the device JTAG testing facility. Table 93. JTAG Pins Pin Name 6 TDI 5 TDO 9 TMS 10 TCK 11 NTRST 6.6.5 Miscellaneous The following table lists the device ...
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Table 94. Miscellaneous Pins (continued) Pin Name 67 REG_EN 69, 70 REG_OUT 24, 51, 52, 72, 73, 74, 75, 76, 77, 78, 79, 96, 97, 98, 99, 100 6.6.6 Power Supply The following table lists the device ...
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Power Supply and Associated Function Although certain function pins may not be used for a specific application, all power supply pins must be connected to their respective voltage input. Table 96. Power Supply Pins and Associated Function Pins Pins ...
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... Pins by Number (VSC8641XKO, VSC8641XKO-03) This section provides a numeric list of the VSC8641XKO and VSC8641XKO-03 pins VDD33 4 VDD33 5 TDO 6 TDI 7 VDD12 8 VDD12 9 TMS 10 TCK 11 NTRST 12 NRESET 13 EEDAT 14 EECLK 15 VDDIOMICRO 16 MDINT 17 MDC 18 MDIO 19 VDD12 20 VDD12 21 CRS 22 COL 23 VDDIOMAC VSS 26 RX_DV 27 RX_ER 28 RXD7 29 RXD6 ...
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... Pins by Name (VSC8641XKO, VSC8641XKO-03) This section provides an alphabetical list of the VSC8641XKO and VSC8641XKO-03 pins. CMODE0 CMODE1 CMODE2 CMODE3 CMODE4 COL CRS EECLK EEDAT GTX_CLK LED0 LED1 LED2 LED3 MDC MDINT MDIO NRESET NSRESET Revision 4.3 August 2009 NTRST OSCEN/CLKOUT 66 PLLMODE ...
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... The VSC8641 device is available in two package types. VSC8641XJF is a lead(Pb)-free, 88-pin, plastic quad flat no-lead (QFN) package with an exposed pad × body size, 0.4 mm pin pitch, and 0.9 mm maximum height. VSC8641XKO and VSC8641XKO-03 are packaged in a 100-pin, plastic low-profile quad flat package (LQFP) with an exposed pad × ...
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Figure 30. Package Drawing for VSC8641XJF Top View D Pin 1 identification 0.42 ±0.18 Side View 12° Notes 1. All dimensions and tolerances are in millimeters (mm). 2. Dimension applies to plated terminal and is ...
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... Figure 31. Package Drawing for VSC8641XKO and VSC8641XKO-03 Top View 100 Side View See Detail A Detail Notes 1. All dimensions and tolerances are in millimeters (mm). 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch ...
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... Thermal Resistances Part Order Number VSC8641XJF VSC8641XKO VSC8641XKO-03 1. Simulated on the top of the mold compound with the exposed pad soldered to a ground pad on the PCB. 2. Calculated on the exposed pad soldered to a ground pad on the PCB. To achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described in the JEDEC standard EIA/JESD51 series must be applied ...
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Design Considerations This section explains various issues associated with the VSC8641 device. 8.1 RX_CLK Can Reach as High as 55% Duty Cycle Issue: When register 23, bit (no internal clock skew) for RGMII, then the RX_CLK ...
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PhyWrite (PortNo, 31, 0x52B5); // Select internal register page PhyWrite (PortNo, 16, 0xA7F8); // Request read of internal register PhyWriteMsk (PortNo, 17, 0x0018, 0x0018); // Set for forced 100BASE-TX PhyWriteMsk (PortNo, 18, 0, 0); // Necessary read & re-write register ...
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PhyWrite (PortNo, 16, 0x87b4); // Necessary write of internal register PhyWrite (PortNo, 16, 0xa794); // Necessary write of internal register reg = PhyRead (PortNo, 18); // Read internal reg. and assign it to var. PhyWrite (PortNo, 18, reg); // Necessary ...
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On-Chip Pull-up Resistor Violation Issue: According to the IEEE standard 802.3, the MDIO pin on a slave device should be an open-drain pad type and drive a low value onto the MDIO shared bus. The MDIO shared bus should ...
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Harmonics at 30 MHz and 50 MHz Marginally Violate Specification Issue: The IEEE 802.3 specification states that in 10BASE-T mode, when the DO circuit is driven by an all-ones, Manchester-encoded signal, any harmonic measured on the TD circuit ...
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Logical Assign value to variable PHY_Write (PortNo, 31, 0x52b5); PHY_Write (PortNo, 16, 0xa7fa); // Necessary write of internal register reg = PHY_Read (PortNo, 18); // Read internal register and assign it to var. PHY_Write (PortNo, ...
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... The VSC8641 device is available in two package types. VSC8641XJF is a lead(Pb)-free, 88-pin, plastic quad flat no-lead (QFN) package with an exposed pad × body size, 0.4 mm pin pitch, and 0.9 mm maximum height. VSC8641XKO and VSC8641XKO-03 are packaged in a 100-pin, plastic low-profile quad flat package (LQFP) with an exposed pad × ...