VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet - Page 14

• Manufacturer Part Number: VSC8641XKO
• Description: IC PHY 10/100/1000 100-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8641XKO

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Case: TQFP
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1031

Revision 4.3
August 2009
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The VSC8641 device switches between the low-power state and LP wake-up state
every two seconds; the rate is not programmable, as was originally stated.
In the link partner wake-up state, the device sends FLP bursts for two seconds;
they are not limited to three bursts, as was originally stated.
In the description of the PHY address for the serial management interface (SMI), a
statement was removed that bits 2:0 represent the PHY of the device being
addressed.
For the enhanced LED method, controlled by MII Register 16E, two of the LED
modes have changed. Mode 11, TX activity, and mode 13, RX activity, are now both
reserved.
In the description of the far-end loopback testing feature, the controlling register
bit was corrected from 23.3 to 27E.10.
For the JTAG interface instructions EXTEST and SAMPLE/PRELOAD, the values for
register width were modified from TBD to 69.
For the Mode Control register (address 0), when bit 11 (power-down) is set, RGMII
in-band signaling will not function.
In the Identifier 2 register (address 3), which enables device identification, the
default for bits 9:4 was modified from TBD to 000011.
In the LED Control register (address 27), the name for bits 2 and 1 was corrected
from “link/activity” to simply “activity.”
In the ActiPHY Control (address 20E), bit 5 was reassigned from being reserved to
being the MAC RX_CLK disable parameter.
In the Extended PHY Control 5 register (address 27E), the settings have changed
for bits 8:6 and 5:3 (100BASE-TX and 1000BASE-T transmitter amplitude control).
For bits 8:6 (100BASE-TX), the setting 011 changed from +5 amplitude to
reserved, making bit setting 010 (+4 amplitude) the largest. For bits 5:3
(1000BASE-T), the setting 011 changed from +3 amplitude to reserved, making bit
setting 010 (+2 amplitude) the largest.
For added clarity, the table that lists device functions and related CMODE pins now
references the associated register and bit for each function.
For the EEPROM Configuration Contents table, some address locations were added
and the introductory text was corrected.
For the DC electrical specifications with VDDIO at 3.3 V and with VDDIO at 2.5 V, an
additional condition was added. The specifications may be considered valid only
when VDDREG = 3.3 V.
The current consumption specifications were replaced with a new set of
specifications.
In the recommended operating conditions, the minimum and maximum values
were modified for the VDDIOMICRO, VDDIOMAC, and VDD33 parameters at 3.3 V.
For all of these parameters, the minimum changed from 3.13 V to 3.0 V and the
maximum changed from 3.47 V to 3.6 V. The VDDREG parameter was added to the
recommended operating conditions.
VSC8641 Datasheet
Revision History
Page 14