VSC8641XKO Vitesse Semiconductor Corp, VSC8641XKO Datasheet - Page 27

• Manufacturer Part Number: VSC8641XKO
• Description: IC PHY 10/100/1000 100-LQFP
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8641XKO

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 2.5V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Case: TQFP
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1031

3.10
Revision 4.3
August 2009
4. If the VSC8641 PHY reports that the LP needs PoE, the Ethernet switch must enable
5. The PHY automatically disables inline powered device detection if the VSC8641
6. In the event of a link failure (indicated when VSC8641 device register bit 1.2 reads
ActiPHY Power Management
In addition to the IEEE-specified power-down control bit (device register bit 0.11), the
device also includes an ActiPHY™ power management mode for each PHY. This mode
enables support for power-sensitive applications such as laptop computers with Wake-
on-LAN™ capability. It utilizes a signal-detect function that monitors the media
interface for the presence of a link to determine when to automatically power-down the
PHY. The PHY “wakes up” at a programmable interval and attempts to “wake up” the
link partner PHY by sending a burst of FLP over copper media.
The ActiPHY power management mode in the VSC8641 device can be enabled during
normal operation at any time by setting register bit 23.5 to 1.
There are three operating states possible when ActiPHY mode is enabled:
•
•
•
The VSC8641 device switches between the low-power state and LP wake-up state every
two seconds until signal energy is detected on the media interface pins. When signal
energy is detected, the PHY enters the normal operating state. If the PHY is in its
normal operating state and the link fails, the PHY returns to the low-power state after
the link status time-out timer has expired. After reset, the PHY enters the low-power
state.
When auto-negotiation is enabled in the PHY, the ActiPHY state machine operates as
described. If auto-negotiation is disabled and the link is forced to 10BT or 100BTX
modes while the PHY is in its low-power state, the PHY continues to transition between
the low-power and LP wake-up states until signal energy is detected on the media pins.
At that time, the PHY transitions to the normal operating state and stays in that state
even when the link is dropped. If auto-negotiation is disabled while the PHY is in the
normal operation state, the PHY stays in that state when the link is dropped and does
not transition back to the low-power state.
The following illustration shows the relationship between ActiPHY states and timers.
cleared and the interrupt de-asserted after the read.
If an LP device does not loop back the FLP after a specific time, VSC8641 device
register bit 23E.9:8 automatically resets to 10.
inline power on this port, externally of the PHY.
device register bit 23E.9:8 automatically resets to 10, and then automatically
changes to its normal auto-negotiation process. A link is then auto-negotiated and
established when the link status bit is set (register bit 1.2 is set to 1).
0), the inline power should be disabled to the inline powered device external to the
PHY. The VSC8641 PHY disables its normal auto-negotiation process and re-enables
its inline powered device detection mode.
Low-power state
LP wake-up state
Normal operating state (link-up state)
Functional Descriptions
VSC8641 Datasheet
Page 27