TP3420AV National Semiconductor, TP3420AV Datasheet - Page 7

• Manufacturer Part Number: TP3420AV
• Manufacturer: National Semiconductor

Specifications of TP3420AV

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
DIGITAL SYSTEM INTERFACE
The Digital System Interface (DSI) on the TP3420A com-
bines “B” and “D” channel data onto common pins to provide
maximum flexibility with minimum pin count. Several multi-
plexed formats of the B and D channel data are available as
shown in Figure 3 . Selection is made via the Control Regis-
ter.
NTA, NTF and TES modes: at this interface, phase skew be-
tween transmit and receive frames may be accommodated
when the device is a slave at the Digital Interface (NT and
TES Modes) since separate frame sync inputs ( Figure 3 ),
FS
counter which gates the transfer of B1 and B2 channels in
consecutive time-slots across the digital interface. The serial
shift rate is determined by the BCLK input, and may be any
multiple of 8 kHz from 256 kHz to 4.096 MHz. Thus, for ap-
plications on a PABX line-card (in NT mode), the “B” and “D”
channel slots can be interfaced to a TDM bus and assigned
to a time-slot.
TEM mode: in TE Master Mode (TEM), FS
ure 4 ) indicating the start of both transmit and receive “B”
channel data transfers. BCLK is also an output at the serial
data shift rate, which is dependent on the format selected,
see Table 5 .
TES mode: for applications such as the network side of an
NT-2, e.g. a PBX trunk card, the TE Slave (TES) Mode is
provided. This “slave-slave” mode allows the transmission
side of the device to be a slave to the received frame timing,
while the Digital System Interface is also in a slave mode i.e.
FS
includes elastic buffers which allow any arbitrary phase rela-
tionship between each FS input and the received I.430
frame.
JITTER ABSORPTION AND PHASE WANDER BUFFERS
The TP3420A has an improved serial data buffer circuit to
handle larger amounts of phase wander exceeding the
specification of 18 µs pk-to-pk, regardless of the phase dif-
ference between the transmit and receive frames. A SLIP in-
dicator interrupt is generated to inform the CPU if the phase
deviation between two clocks exceeds the boundary of the
circuit, causing the data buffers to adjust the internal delay to
accommodate this. Under some, but not all, circumstances
this will result in data errors as the slip occurs. Separate in-
terrupt status values (SLIP — TX and SLIP — RX) indicate
the clock slippage in the transmit buffer or the receiver buffer.
TES Mode also provides a synchronized clock output
(SCLK) which is phase-locked to the received line signal;
SCLK may be used as the BCLK source.
Format
a
a
, FS
and FS
1
2
b
and BCLK are inputs. The Digital System Interface
b
, are provided. Each of these synchronizes a
(Output) (Note 5)
TABLE 3. DSI Format Rates
DSI Master
2.048 MHz
BLCK as
256 kHz
256 kHz–4.096 MHz
256 kHz–4.096 MHz
(Continued)
a
DSI Slave
BCLK as
is an output ( Fig-
(Input)
7
Note 5: also SCLK output in TES Mode.
MICROWIRE CONTROL INTERFACE
A serial interface, which can be clocked independently from
the “B” and “D” channel system interface, is provided for mi-
croprocessor control of various functions in the TP3420. This
port can be used when the device is powered up or powered
down. All data transfers consist of a single byte shifted into
the Control Register via the CI pin, simultaneous with a
single byte shifted out from the Status Register via the CO
pin.
Data shifts in to CI on rising edges of CCLK and out from CO
on falling edges when CS is pulled low for 8 cycles of CCLK.
An Interrupt output, INT goes low to alert the microprocessor
whenever a change occurs in one or more of the conditions
indicated in the Status Register. This latched output is
cleared to a high impedance state by the first rising CCLK
edge after CS goes low. Interrupt Source(s) occurring while
another is still pending are stored in a stack and read in se-
quence, by causing another interrupt at the end of the cur-
rent CS cycle (INT can go low only when CS is high). When
reading the Status Register the CI input is also enabled,
therefore a “dummy” command e.g. NOP(X’FF) must be
loaded into CI as CO is read.
Each source of an Interrupt event ( e.g., EI, AI, SLIP) in the
device has an internal latch, such that the occurrence of that
event is stored until read from the status register. Multiple
events will be reported in turn by the device in a circular
manner. There is no priority criteria. If multiple occurrences
of the same event occur ( e.g., EI, followed by AI and then EI)
and if left unserviced, than the second occurrence (of EI in
this example) will over-write the first. Also if a multiframe in-
terrupt such as MFR1 interrupt is not serviced before a sec-
ond occurrence of the MFR1 interrupt, then the second value
in the M1–M4 bits will overwrite the first. The DI interrupt
clears all pending interrupts and indicating the reset state of
the device. The LSD interrupt is generated independently
and is only valid while the device is in low power mode
(PDN). A PUP command resets the line signal detect circuit
and the LSD interrupt. A PDN command resets and
re-enables the LSD circuit and interrupt.
Figure 5 shows the timing for this interface, and Table 4 and
Table 5 list the control functions and status indicators.
FLEXIBLE MICROWIRE PORT
The MICROWIRE port of the TP3420A has been enhanced
such that it can connect to standard MICROWIRE master
devices (such as National’s microcontrollers of the HPC and
COP families) as well as the SCP interface master from the
Motorola microcontroller family. SCP is the Serial Control
Port on devices such as the MC68302 or the MC145488
HDLC. See the MICROWIRE port timing diagram and the
applications section.
Format
3
4
(Output) (Note 5)
DSI Master
2.56 MHz
BLCK as
512 kHz
512 kHz–4.096 MHz
256 kHz–4.096 MHz
DSI Slave
BCLK as
(Input)
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