TP3420AV National Semiconductor, TP3420AV Datasheet - Page 2

• Manufacturer Part Number: TP3420AV
• Manufacturer: National Semiconductor

Specifications of TP3420AV

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

www.national.com
Block Diagram
Connection Diagrams
See NS Package Number J20A or N20A
Order Number TP3420AJ or TP3420AN
See NS Package Number V20A
Order Number TP3420AV
TP3420A SID
TP3420A SID
Top View
DS009143-2
DS009143-20
2
Pin Descriptions
GND
V
MCLK/XTAL
XTAL2
BCLK
CC
Name
Negative power supply pin, normally 0V
(ground). All analog and digital signals
are referenced to this pin.
Positive power supply input, which must
be +5V
The 15.36 MHz Master Clock input, which
requires either a crystal (Note 1) to be
tied between this pin and XTAL2, or a
CMOS logic level clock input from a
stable source. When using a crystal, a
total of 33 pF load capacitance to GND
must also be connected. (Note 2)
The output of the crystal oscillator, which
should be connected to one end of the
crystal, and 33 pF of load capacitance to
GND. (Note 2) If using an external master
Clock via the MCLK pin, leave the XTAL2
pin unconnected.
The Bit Clock pin, which determines the
data shift rate for “B” and “D” channel
data at the digital interface. When NT
mode or TES mode is selected, BCLK is
a TTL/CMOS input which may be any
multiple of 8 kHz from 256 kHz to 4.096
MHz. It need not be synchronous with
MCLK.
When TEM mode is selected, this pin is a
CMOS output at frequency selected by
the Digital Interface Format. This clock is
phase-locked to the received line signal
and is synchronous with the data on B
and B
r
.
±
5% relative to GND.
Description
DS009143-1
x