TP3420AV National Semiconductor, TP3420AV Datasheet - Page 13

• Manufacturer Part Number: TP3420AV
• Manufacturer: National Semiconductor

Specifications of TP3420AV

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
AI
EI
DI
MFR1
MFR2
MFC
RMFE
SLIP
NOC
NOCST This status response occurs only after the ENST
CONTROL REGISTER INSTRUCTIONS
ACTIVATION/DEACTIVATION
PUP This power-up command enables all analog circuitry,
PDN This power-down command immediately forces the
starts the XTAL and resets the state machines to the
de-activated state, i.e. transmitting INFO 0 (no signal).
It also inhibits the LSD output.
device to a low power state, without sequencing
through any of the de-activation states. It should
therefore only be used after the TP3420A has been
put in a known state, e.g. in a TE after a DI status in-
a packet in the D channel, a received E bit does
not match the last transmitted D bit, indicating a
lost collision.
This interrupt indicates that the interface has been
successfully Activated in response to an Activation
Request.
Set when loss of frame alignment is detected.
If set, indicates that the interface has been Deacti-
vated.
This interrupt indicates when the Multiframe
SC1/Q channel data buffer requires servicing, see
Multiframe Maintenance section. The MID1 com-
mand disables this interrupt.
This interrupt indicates when the Multiframe SC2
channel data buffer requires servicing, see Multi-
frame Maintenance section. The MID2 command
disables this interrupt.
This status interrupt provides a transmit multiframe
clock. It can be selected to occur on every multi-
frame boundary (5 ms) by the MFC1E command
or on each 6 multiframe boundary (30 ms) by the
MFC6E command. This interrupt can be used to
synchronize the SC1/Q and SC2 multiframe trans-
mit messages.
A bipolar Violation or DC balance error causes this
Receive Multiframe Error Interrupt in both NT and
TE modes. At the NT end, upon receiving the
RMFE interrupt, the local microcontroller must in-
form the TEs with a FECV message (via the
MFT1H register). The NT or the TE end can keep
a count of RMFE interrupts to monitor the line
block error rate at its receiver.
This interrupt indicates if the clock phase shift in
the jitter/wander buffers exceeded the phase shift
limit and changed the internal data buffer delay to
accommodate it. One interrupt is generated and is
coded as X’09 for Tx buffer slip: X’0A for Rx buffer
slip: and X’0B for both Tx and Rx buffer slip.
This NOC status is returned for every command
when there is no change of status to be reported.
It is read in the power-up default state and after the
DISST command. No interrupt is generated.
command. The NOCST status is returned in re-
sponse to any subsequent command when there
is no status change that needs to be reported with
an interrupt. It contains the device activation state
information, see the section on Activation State
machine access.
(Continued)
13
AR
DR
FI2
MMA Intended for test equipment applications, this instruc-
DEVICE MODES
NTA NT Mode, Adaptive Sampling should be selected
NTF NT Mode Fixed Sampling may be selected when the
TEM TE Mode DSI Master should be selected when the de-
TES TE
when the device is in an NT on any wiring configura-
tion up to the maximum specified length for operation.
Multiple terminals, if required, must be grouped within
approximately 100 meters of each other (depending
on cable capacitance, see I.430). The Digital System
Interface is a slave to external BCLK and FS sources.
device is in an NT on a passive bus wiring configura-
tion up to approximately 200 meters in length (de-
pending on cable type). In this mode the receiver
DPLL is disabled and sampling of the received sym-
bols is fixed, to enable multiple terminals (nominally
up to 8) to be connected anywhere along the passive
bus. Again, the DSI is a slave to external BCLK and
FS sources.
vice is in a TE. The TP3420A is then the source of the
BCLK and FS signals, and access to the Transmit D
channel, including the priority and contention resolu-
tion control, is enabled as described in the section on
TE Mode D-Channel Access.
“Slave-slave” mode, should be selected when the de-
vice is used on the T-interface side of an NT-2. The
TP3420A System Interface is then driven by BCLK
and FS sources in the NT-2. Data buffers and a clock
re-synchronizer enable this interface to function with
jittering sources for BCLK and FS. All D Channel ac-
cess control circuitry is disabled, i.e. D Channel data
at the Bx input is continuously transmitted to the line;
there is no monitoring of the D-echo channel from the
network direction, and DREQ instructions are ignored.
Also, the SCLK function is enabled at the DEN
pin.
dication has been reported. It also enables the LSD
circuit.
Activation Request initiates the specified Activation
sequence. It is recommended that an AR be delayed
at least 2 ms after the device is powered-up using the
PUP command.
Deactivation Request, which forces the device
through the appropriate deactivation sequence speci-
fied in I.430. Should be used at the NT end only.
Effective only in NT modes, and only after Activation
has been completed, this instruction forces the NT to
transmit INFO 2 frames instead of INFO 4, normally to
allow testing at the U interface. Provided INFO 3 is still
being received from the TE(s), an AP Status Interrupt
will be generated and loop synchronization main-
tained, but 2B+D transmission is inhibited. To restore
full loop activation, with the NT sending INFO 4, an AR
command is required in the normal way.
tion allows the receive line interface (Li
nected to the TE-to-NT direction twisted pair and to
activate on the received INFO 3 signals while being
the master of the DSI. The received 2B+D can then be
passively monitored (the line transmit output Lo
would not be connected). TE Master mode must be
selected first (TEM).
Mode
DSI
Slave,
otherwise
±
) to be con-
www.national.com
known
x
/SCLK
as
±